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JustOS/linux-6.13/tools/arch/x86/kcpuid/cpuid.csv
justuser 02e73b8cd9 up
2025-01-24 17:00:19 +03:00

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1# SPDX-License-Identifier: CC0-1.0
2# Generator: x86-cpuid-db v1.0
3#
4# Auto-generated file.
5# Please submit all updates and bugfixes to https://x86-cpuid.org
6#
7# The basic row format is:
8# LEAF, SUBLEAVES, reg, bits, short_name , long_description
9# Leaf 0H
10# Maximum standard leaf number + CPU vendor string
11 0, 0, eax, 31:0, max_std_leaf , Highest cpuid standard leaf supported
12 0, 0, ebx, 31:0, cpu_vendorid_0 , CPU vendor ID string bytes 0 - 3
13 0, 0, ecx, 31:0, cpu_vendorid_2 , CPU vendor ID string bytes 8 - 11
14 0, 0, edx, 31:0, cpu_vendorid_1 , CPU vendor ID string bytes 4 - 7
15# Leaf 1H
16# CPU FMS (Family/Model/Stepping) + standard feature flags
17 1, 0, eax, 3:0, stepping , Stepping ID
18 1, 0, eax, 7:4, base_model , Base CPU model ID
19 1, 0, eax, 11:8, base_family_id , Base CPU family ID
20 1, 0, eax, 13:12, cpu_type , CPU type
21 1, 0, eax, 19:16, ext_model , Extended CPU model ID
22 1, 0, eax, 27:20, ext_family , Extended CPU family ID
23 1, 0, ebx, 7:0, brand_id , Brand index
24 1, 0, ebx, 15:8, clflush_size , CLFLUSH instruction cache line size
25 1, 0, ebx, 23:16, n_logical_cpu , Logical CPU (HW threads) count
26 1, 0, ebx, 31:24, local_apic_id , Initial local APIC physical ID
27 1, 0, ecx, 0, pni , Streaming SIMD Extensions 3 (SSE3)
28 1, 0, ecx, 1, pclmulqdq , PCLMULQDQ instruction support
29 1, 0, ecx, 2, dtes64 , 64-bit DS save area
30 1, 0, ecx, 3, monitor , MONITOR/MWAIT support
31 1, 0, ecx, 4, ds_cpl , CPL Qualified Debug Store
32 1, 0, ecx, 5, vmx , Virtual Machine Extensions
33 1, 0, ecx, 6, smx , Safer Mode Extensions
34 1, 0, ecx, 7, est , Enhanced Intel SpeedStep
35 1, 0, ecx, 8, tm2 , Thermal Monitor 2
36 1, 0, ecx, 9, ssse3 , Supplemental SSE3
37 1, 0, ecx, 10, cid , L1 Context ID
38 1, 0, ecx, 11, sdbg , Sillicon Debug
39 1, 0, ecx, 12, fma , FMA extensions using YMM state
40 1, 0, ecx, 13, cx16 , CMPXCHG16B instruction support
41 1, 0, ecx, 14, xtpr , xTPR Update Control
42 1, 0, ecx, 15, pdcm , Perfmon and Debug Capability
43 1, 0, ecx, 17, pcid , Process-context identifiers
44 1, 0, ecx, 18, dca , Direct Cache Access
45 1, 0, ecx, 19, sse4_1 , SSE4.1
46 1, 0, ecx, 20, sse4_2 , SSE4.2
47 1, 0, ecx, 21, x2apic , X2APIC support
48 1, 0, ecx, 22, movbe , MOVBE instruction support
49 1, 0, ecx, 23, popcnt , POPCNT instruction support
50 1, 0, ecx, 24, tsc_deadline_timer , APIC timer one-shot operation
51 1, 0, ecx, 25, aes , AES instructions
52 1, 0, ecx, 26, xsave , XSAVE (and related instructions) support
53 1, 0, ecx, 27, osxsave , XSAVE (and related instructions) are enabled by OS
54 1, 0, ecx, 28, avx , AVX instructions support
55 1, 0, ecx, 29, f16c , Half-precision floating-point conversion support
56 1, 0, ecx, 30, rdrand , RDRAND instruction support
57 1, 0, ecx, 31, guest_status , System is running as guest; (para-)virtualized system
58 1, 0, edx, 0, fpu , Floating-Point Unit on-chip (x87)
59 1, 0, edx, 1, vme , Virtual-8086 Mode Extensions
60 1, 0, edx, 2, de , Debugging Extensions
61 1, 0, edx, 3, pse , Page Size Extension
62 1, 0, edx, 4, tsc , Time Stamp Counter
63 1, 0, edx, 5, msr , Model-Specific Registers (RDMSR and WRMSR support)
64 1, 0, edx, 6, pae , Physical Address Extensions
65 1, 0, edx, 7, mce , Machine Check Exception
66 1, 0, edx, 8, cx8 , CMPXCHG8B instruction
67 1, 0, edx, 9, apic , APIC on-chip
68 1, 0, edx, 11, sep , SYSENTER, SYSEXIT, and associated MSRs
69 1, 0, edx, 12, mtrr , Memory Type Range Registers
70 1, 0, edx, 13, pge , Page Global Extensions
71 1, 0, edx, 14, mca , Machine Check Architecture
72 1, 0, edx, 15, cmov , Conditional Move Instruction
73 1, 0, edx, 16, pat , Page Attribute Table
74 1, 0, edx, 17, pse36 , Page Size Extension (36-bit)
75 1, 0, edx, 18, pn , Processor Serial Number
76 1, 0, edx, 19, clflush , CLFLUSH instruction
77 1, 0, edx, 21, dts , Debug Store
78 1, 0, edx, 22, acpi , Thermal monitor and clock control
79 1, 0, edx, 23, mmx , MMX instructions
80 1, 0, edx, 24, fxsr , FXSAVE and FXRSTOR instructions
81 1, 0, edx, 25, sse , SSE instructions
82 1, 0, edx, 26, sse2 , SSE2 instructions
83 1, 0, edx, 27, ss , Self Snoop
84 1, 0, edx, 28, ht , Hyper-threading
85 1, 0, edx, 29, tm , Thermal Monitor
86 1, 0, edx, 30, ia64 , Legacy IA-64 (Itanium) support bit, now resreved
87 1, 0, edx, 31, pbe , Pending Break Enable
88# Leaf 2H
89# Intel cache and TLB information one-byte descriptors
90 2, 0, eax, 7:0, iteration_count , Number of times this CPUD leaf must be queried
91 2, 0, eax, 15:8, desc1 , Descriptor #1
92 2, 0, eax, 23:16, desc2 , Descriptor #2
93 2, 0, eax, 30:24, desc3 , Descriptor #3
94 2, 0, eax, 31, eax_invalid , Descriptors 1-3 are invalid if set
95 2, 0, ebx, 7:0, desc4 , Descriptor #4
96 2, 0, ebx, 15:8, desc5 , Descriptor #5
97 2, 0, ebx, 23:16, desc6 , Descriptor #6
98 2, 0, ebx, 30:24, desc7 , Descriptor #7
99 2, 0, ebx, 31, ebx_invalid , Descriptors 4-7 are invalid if set
100 2, 0, ecx, 7:0, desc8 , Descriptor #8
101 2, 0, ecx, 15:8, desc9 , Descriptor #9
102 2, 0, ecx, 23:16, desc10 , Descriptor #10
103 2, 0, ecx, 30:24, desc11 , Descriptor #11
104 2, 0, ecx, 31, ecx_invalid , Descriptors 8-11 are invalid if set
105 2, 0, edx, 7:0, desc12 , Descriptor #12
106 2, 0, edx, 15:8, desc13 , Descriptor #13
107 2, 0, edx, 23:16, desc14 , Descriptor #14
108 2, 0, edx, 30:24, desc15 , Descriptor #15
109 2, 0, edx, 31, edx_invalid , Descriptors 12-15 are invalid if set
110# Leaf 4H
111# Intel deterministic cache parameters
112 4, 31:0, eax, 4:0, cache_type , Cache type field
113 4, 31:0, eax, 7:5, cache_level , Cache level (1-based)
114 4, 31:0, eax, 8, cache_self_init , Self-initialializing cache level
115 4, 31:0, eax, 9, fully_associative , Fully-associative cache
116 4, 31:0, eax, 25:14, num_threads_sharing , Number logical CPUs sharing this cache
117 4, 31:0, eax, 31:26, num_cores_on_die , Number of cores in the physical package
118 4, 31:0, ebx, 11:0, cache_linesize , System coherency line size (0-based)
119 4, 31:0, ebx, 21:12, cache_npartitions , Physical line partitions (0-based)
120 4, 31:0, ebx, 31:22, cache_nways , Ways of associativity (0-based)
121 4, 31:0, ecx, 30:0, cache_nsets , Cache number of sets (0-based)
122 4, 31:0, edx, 0, wbinvd_rll_no_guarantee, WBINVD/INVD not guaranteed for Remote Lower-Level caches
123 4, 31:0, edx, 1, ll_inclusive , Cache is inclusive of Lower-Level caches
124 4, 31:0, edx, 2, complex_indexing , Not a direct-mapped cache (complex function)
125# Leaf 5H
126# MONITOR/MWAIT instructions enumeration
127 5, 0, eax, 15:0, min_mon_size , Smallest monitor-line size, in bytes
128 5, 0, ebx, 15:0, max_mon_size , Largest monitor-line size, in bytes
129 5, 0, ecx, 0, mwait_ext , Enumeration of MONITOR/MWAIT extensions is supported
130 5, 0, ecx, 1, mwait_irq_break , Interrupts as a break-event for MWAIT is supported
131 5, 0, edx, 3:0, n_c0_substates , Number of C0 sub C-states supported using MWAIT
132 5, 0, edx, 7:4, n_c1_substates , Number of C1 sub C-states supported using MWAIT
133 5, 0, edx, 11:8, n_c2_substates , Number of C2 sub C-states supported using MWAIT
134 5, 0, edx, 15:12, n_c3_substates , Number of C3 sub C-states supported using MWAIT
135 5, 0, edx, 19:16, n_c4_substates , Number of C4 sub C-states supported using MWAIT
136 5, 0, edx, 23:20, n_c5_substates , Number of C5 sub C-states supported using MWAIT
137 5, 0, edx, 27:24, n_c6_substates , Number of C6 sub C-states supported using MWAIT
138 5, 0, edx, 31:28, n_c7_substates , Number of C7 sub C-states supported using MWAIT
139# Leaf 6H
140# Thermal and Power Management enumeration
141 6, 0, eax, 0, dtherm , Digital temprature sensor
142 6, 0, eax, 1, turbo_boost , Intel Turbo Boost
143 6, 0, eax, 2, arat , Always-Running APIC Timer (not affected by p-state)
144 6, 0, eax, 4, pln , Power Limit Notification (PLN) event
145 6, 0, eax, 5, ecmd , Clock modulation duty cycle extension
146 6, 0, eax, 6, pts , Package thermal management
147 6, 0, eax, 7, hwp , HWP (Hardware P-states) base registers are supported
148 6, 0, eax, 8, hwp_notify , HWP notification (IA32_HWP_INTERRUPT MSR)
149 6, 0, eax, 9, hwp_act_window , HWP activity window (IA32_HWP_REQUEST[bits 41:32]) supported
150 6, 0, eax, 10, hwp_epp , HWP Energy Performance Preference
151 6, 0, eax, 11, hwp_pkg_req , HWP Package Level Request
152 6, 0, eax, 13, hdc_base_regs , HDC base registers are supported
153 6, 0, eax, 14, turbo_boost_3_0 , Intel Turbo Boost Max 3.0
154 6, 0, eax, 15, hwp_capabilities , HWP Highest Performance change
155 6, 0, eax, 16, hwp_peci_override , HWP PECI override
156 6, 0, eax, 17, hwp_flexible , Flexible HWP
157 6, 0, eax, 18, hwp_fast , IA32_HWP_REQUEST MSR fast access mode
158 6, 0, eax, 19, hfi , HW_FEEDBACK MSRs supported
159 6, 0, eax, 20, hwp_ignore_idle , Ignoring idle logical CPU HWP req is supported
160 6, 0, eax, 23, thread_director , Intel thread director support
161 6, 0, eax, 24, therm_interrupt_bit25 , IA32_THERM_INTERRUPT MSR bit 25 is supported
162 6, 0, ebx, 3:0, n_therm_thresholds , Digital thermometer thresholds
163 6, 0, ecx, 0, aperfmperf , MPERF/APERF MSRs (effective frequency interface)
164 6, 0, ecx, 3, epb , IA32_ENERGY_PERF_BIAS MSR support
165 6, 0, ecx, 15:8, thrd_director_nclasses , Number of classes, Intel thread director
166 6, 0, edx, 0, perfcap_reporting , Performance capability reporting
167 6, 0, edx, 1, encap_reporting , Energy efficiency capability reporting
168 6, 0, edx, 11:8, feedback_sz , HW feedback interface struct size, in 4K pages
169 6, 0, edx, 31:16, this_lcpu_hwfdbk_idx , This logical CPU index @ HW feedback struct, 0-based
170# Leaf 7H
171# Extended CPU features enumeration
172 7, 0, eax, 31:0, leaf7_n_subleaves , Number of cpuid 0x7 subleaves
173 7, 0, ebx, 0, fsgsbase , FSBASE/GSBASE read/write support
174 7, 0, ebx, 1, tsc_adjust , IA32_TSC_ADJUST MSR supported
175 7, 0, ebx, 2, sgx , Intel SGX (Software Guard Extensions)
176 7, 0, ebx, 3, bmi1 , Bit manipulation extensions group 1
177 7, 0, ebx, 4, hle , Hardware Lock Elision
178 7, 0, ebx, 5, avx2 , AVX2 instruction set
179 7, 0, ebx, 6, fdp_excptn_only , FPU Data Pointer updated only on x87 exceptions
180 7, 0, ebx, 7, smep , Supervisor Mode Execution Protection
181 7, 0, ebx, 8, bmi2 , Bit manipulation extensions group 2
182 7, 0, ebx, 9, erms , Enhanced REP MOVSB/STOSB
183 7, 0, ebx, 10, invpcid , INVPCID instruction (Invalidate Processor Context ID)
184 7, 0, ebx, 11, rtm , Intel restricted transactional memory
185 7, 0, ebx, 12, cqm , Intel RDT-CMT / AMD Platform-QoS cache monitoring
186 7, 0, ebx, 13, zero_fcs_fds , Deprecated FPU CS/DS (stored as zero)
187 7, 0, ebx, 14, mpx , Intel memory protection extensions
188 7, 0, ebx, 15, rdt_a , Intel RDT / AMD Platform-QoS Enforcemeent
189 7, 0, ebx, 16, avx512f , AVX-512 foundation instructions
190 7, 0, ebx, 17, avx512dq , AVX-512 double/quadword instructions
191 7, 0, ebx, 18, rdseed , RDSEED instruction
192 7, 0, ebx, 19, adx , ADCX/ADOX instructions
193 7, 0, ebx, 20, smap , Supervisor mode access prevention
194 7, 0, ebx, 21, avx512ifma , AVX-512 integer fused multiply add
195 7, 0, ebx, 23, clflushopt , CLFLUSHOPT instruction
196 7, 0, ebx, 24, clwb , CLWB instruction
197 7, 0, ebx, 25, intel_pt , Intel processor trace
198 7, 0, ebx, 26, avx512pf , AVX-512 prefetch instructions
199 7, 0, ebx, 27, avx512er , AVX-512 exponent/reciprocal instrs
200 7, 0, ebx, 28, avx512cd , AVX-512 conflict detection instrs
201 7, 0, ebx, 29, sha_ni , SHA/SHA256 instructions
202 7, 0, ebx, 30, avx512bw , AVX-512 BW (byte/word granular) instructions
203 7, 0, ebx, 31, avx512vl , AVX-512 VL (128/256 vector length) extensions
204 7, 0, ecx, 0, prefetchwt1 , PREFETCHWT1 (Intel Xeon Phi only)
205 7, 0, ecx, 1, avx512vbmi , AVX-512 Vector byte manipulation instrs
206 7, 0, ecx, 2, umip , User mode instruction protection
207 7, 0, ecx, 3, pku , Protection keys for user-space
208 7, 0, ecx, 4, ospke , OS protection keys enable
209 7, 0, ecx, 5, waitpkg , WAITPKG instructions
210 7, 0, ecx, 6, avx512_vbmi2 , AVX-512 vector byte manipulation instrs group 2
211 7, 0, ecx, 7, cet_ss , CET shadow stack features
212 7, 0, ecx, 8, gfni , Galois field new instructions
213 7, 0, ecx, 9, vaes , Vector AES instrs
214 7, 0, ecx, 10, vpclmulqdq , VPCLMULQDQ 256-bit instruction support
215 7, 0, ecx, 11, avx512_vnni , Vector neural network instructions
216 7, 0, ecx, 12, avx512_bitalg , AVX-512 bit count/shiffle
217 7, 0, ecx, 13, tme , Intel total memory encryption
218 7, 0, ecx, 14, avx512_vpopcntdq , AVX-512: POPCNT for vectors of DW/QW
219 7, 0, ecx, 16, la57 , 57-bit linear addreses (five-level paging)
220 7, 0, ecx, 21:17, mawau_val_lm , BNDLDX/BNDSTX MAWAU value in 64-bit mode
221 7, 0, ecx, 22, rdpid , RDPID instruction
222 7, 0, ecx, 23, key_locker , Intel key locker support
223 7, 0, ecx, 24, bus_lock_detect , OS bus-lock detection
224 7, 0, ecx, 25, cldemote , CLDEMOTE instruction
225 7, 0, ecx, 27, movdiri , MOVDIRI instruction
226 7, 0, ecx, 28, movdir64b , MOVDIR64B instruction
227 7, 0, ecx, 29, enqcmd , Enqueue stores supported (ENQCMD{,S})
228 7, 0, ecx, 30, sgx_lc , Intel SGX launch configuration
229 7, 0, ecx, 31, pks , Protection keys for supervisor-mode pages
230 7, 0, edx, 1, sgx_keys , Intel SGX attestation services
231 7, 0, edx, 2, avx512_4vnniw , AVX-512 neural network instructions
232 7, 0, edx, 3, avx512_4fmaps , AVX-512 multiply accumulation single precision
233 7, 0, edx, 4, fsrm , Fast short REP MOV
234 7, 0, edx, 5, uintr , CPU supports user interrupts
235 7, 0, edx, 8, avx512_vp2intersect , VP2INTERSECT{D,Q} instructions
236 7, 0, edx, 9, srdbs_ctrl , SRBDS mitigation MSR available
237 7, 0, edx, 10, md_clear , VERW MD_CLEAR microcode support
238 7, 0, edx, 11, rtm_always_abort , XBEGIN (RTM transaction) always aborts
239 7, 0, edx, 13, tsx_force_abort , MSR TSX_FORCE_ABORT, RTM_ABORT bit, supported
240 7, 0, edx, 14, serialize , SERIALIZE instruction
241 7, 0, edx, 15, hybrid_cpu , The CPU is identified as a 'hybrid part'
242 7, 0, edx, 16, tsxldtrk , TSX suspend/resume load address tracking
243 7, 0, edx, 18, pconfig , PCONFIG instruction
244 7, 0, edx, 19, arch_lbr , Intel architectural LBRs
245 7, 0, edx, 20, ibt , CET indirect branch tracking
246 7, 0, edx, 22, amx_bf16 , AMX-BF16: tile bfloat16 support
247 7, 0, edx, 23, avx512_fp16 , AVX-512 FP16 instructions
248 7, 0, edx, 24, amx_tile , AMX-TILE: tile architecture support
249 7, 0, edx, 25, amx_int8 , AMX-INT8: tile 8-bit integer support
250 7, 0, edx, 26, spec_ctrl , Speculation Control (IBRS/IBPB: indirect branch restrictions)
251 7, 0, edx, 27, intel_stibp , Single thread indirect branch predictors
252 7, 0, edx, 28, flush_l1d , FLUSH L1D cache: IA32_FLUSH_CMD MSR
253 7, 0, edx, 29, arch_capabilities , Intel IA32_ARCH_CAPABILITIES MSR
254 7, 0, edx, 30, core_capabilities , IA32_CORE_CAPABILITIES MSR
255 7, 0, edx, 31, spec_ctrl_ssbd , Speculative store bypass disable
256 7, 1, eax, 4, avx_vnni , AVX-VNNI instructions
257 7, 1, eax, 5, avx512_bf16 , AVX-512 bFloat16 instructions
258 7, 1, eax, 6, lass , Linear address space separation
259 7, 1, eax, 7, cmpccxadd , CMPccXADD instructions
260 7, 1, eax, 8, arch_perfmon_ext , ArchPerfmonExt: CPUID leaf 0x23 is supported
261 7, 1, eax, 10, fzrm , Fast zero-length REP MOVSB
262 7, 1, eax, 11, fsrs , Fast short REP STOSB
263 7, 1, eax, 12, fsrc , Fast Short REP CMPSB/SCASB
264 7, 1, eax, 17, fred , FRED: Flexible return and event delivery transitions
265 7, 1, eax, 18, lkgs , LKGS: Load 'kernel' (userspace) GS
266 7, 1, eax, 19, wrmsrns , WRMSRNS instr (WRMSR-non-serializing)
267 7, 1, eax, 21, amx_fp16 , AMX-FP16: FP16 tile operations
268 7, 1, eax, 22, hreset , History reset support
269 7, 1, eax, 23, avx_ifma , Integer fused multiply add
270 7, 1, eax, 26, lam , Linear address masking
271 7, 1, eax, 27, rd_wr_msrlist , RDMSRLIST/WRMSRLIST instructions
272 7, 1, ebx, 0, intel_ppin , Protected processor inventory number (PPIN{,_CTL} MSRs)
273 7, 1, edx, 4, avx_vnni_int8 , AVX-VNNI-INT8 instructions
274 7, 1, edx, 5, avx_ne_convert , AVX-NE-CONVERT instructions
275 7, 1, edx, 8, amx_complex , AMX-COMPLEX instructions (starting from Granite Rapids)
276 7, 1, edx, 14, prefetchit_0_1 , PREFETCHIT0/1 instructions
277 7, 1, edx, 18, cet_sss , CET supervisor shadow stacks safe to use
278 7, 2, edx, 0, intel_psfd , Intel predictive store forward disable
279 7, 2, edx, 1, ipred_ctrl , MSR bits IA32_SPEC_CTRL.IPRED_DIS_{U,S}
280 7, 2, edx, 2, rrsba_ctrl , MSR bits IA32_SPEC_CTRL.RRSBA_DIS_{U,S}
281 7, 2, edx, 3, ddp_ctrl , MSR bit IA32_SPEC_CTRL.DDPD_U
282 7, 2, edx, 4, bhi_ctrl , MSR bit IA32_SPEC_CTRL.BHI_DIS_S
283 7, 2, edx, 5, mcdt_no , MCDT mitigation not needed
284 7, 2, edx, 6, uclock_disable , UC-lock disable is supported
285# Leaf 9H
286# Intel DCA (Direct Cache Access) enumeration
287 9, 0, eax, 0, dca_enabled_in_bios , DCA is enabled in BIOS
288# Leaf AH
289# Intel PMU (Performance Monitoring Unit) enumeration
290 0xa, 0, eax, 7:0, pmu_version , Performance monitoring unit version ID
291 0xa, 0, eax, 15:8, pmu_n_gcounters , Number of general PMU counters per logical CPU
292 0xa, 0, eax, 23:16, pmu_gcounters_nbits , Bitwidth of PMU general counters
293 0xa, 0, eax, 31:24, pmu_cpuid_ebx_bits , Length of cpuid leaf 0xa EBX bit vector
294 0xa, 0, ebx, 0, no_core_cycle_evt , Core cycle event not available
295 0xa, 0, ebx, 1, no_insn_retired_evt , Instruction retired event not available
296 0xa, 0, ebx, 2, no_refcycle_evt , Reference cycles event not available
297 0xa, 0, ebx, 3, no_llc_ref_evt , LLC-reference event not available
298 0xa, 0, ebx, 4, no_llc_miss_evt , LLC-misses event not available
299 0xa, 0, ebx, 5, no_br_insn_ret_evt , Branch instruction retired event not available
300 0xa, 0, ebx, 6, no_br_mispredict_evt , Branch mispredict retired event not available
301 0xa, 0, ebx, 7, no_td_slots_evt , Topdown slots event not available
302 0xa, 0, ecx, 31:0, pmu_fcounters_bitmap , Fixed-function PMU counters support bitmap
303 0xa, 0, edx, 4:0, pmu_n_fcounters , Number of fixed PMU counters
304 0xa, 0, edx, 12:5, pmu_fcounters_nbits , Bitwidth of PMU fixed counters
305 0xa, 0, edx, 15, anythread_depr , AnyThread deprecation
306# Leaf BH
307# CPUs v1 extended topology enumeration
308 0xb, 1:0, eax, 4:0, x2apic_id_shift , Bit width of this level (previous levels inclusive)
309 0xb, 1:0, ebx, 15:0, domain_lcpus_count , Logical CPUs count across all instances of this domain
310 0xb, 1:0, ecx, 7:0, domain_nr , This domain level (subleaf ID)
311 0xb, 1:0, ecx, 15:8, domain_type , This domain type
312 0xb, 1:0, edx, 31:0, x2apic_id , x2APIC ID of current logical CPU
313# Leaf DH
314# Processor extended state enumeration
315 0xd, 0, eax, 0, xcr0_x87 , XCR0.X87 (bit 0) supported
316 0xd, 0, eax, 1, xcr0_sse , XCR0.SEE (bit 1) supported
317 0xd, 0, eax, 2, xcr0_avx , XCR0.AVX (bit 2) supported
318 0xd, 0, eax, 3, xcr0_mpx_bndregs , XCR0.BNDREGS (bit 3) supported (MPX BND0-BND3 regs)
319 0xd, 0, eax, 4, xcr0_mpx_bndcsr , XCR0.BNDCSR (bit 4) supported (MPX BNDCFGU/BNDSTATUS regs)
320 0xd, 0, eax, 5, xcr0_avx512_opmask , XCR0.OPMASK (bit 5) supported (AVX-512 k0-k7 regs)
321 0xd, 0, eax, 6, xcr0_avx512_zmm_hi256 , XCR0.ZMM_Hi256 (bit 6) supported (AVX-512 ZMM0->ZMM7/15 regs)
322 0xd, 0, eax, 7, xcr0_avx512_hi16_zmm , XCR0.HI16_ZMM (bit 7) supported (AVX-512 ZMM16->ZMM31 regs)
323 0xd, 0, eax, 9, xcr0_pkru , XCR0.PKRU (bit 9) supported (XSAVE PKRU reg)
324 0xd, 0, eax, 11, xcr0_cet_u , AMD XCR0.CET_U (bit 11) supported (CET supervisor state)
325 0xd, 0, eax, 12, xcr0_cet_s , AMD XCR0.CET_S (bit 12) support (CET user state)
326 0xd, 0, eax, 17, xcr0_tileconfig , XCR0.TILECONFIG (bit 17) supported (AMX can manage TILECONFIG)
327 0xd, 0, eax, 18, xcr0_tiledata , XCR0.TILEDATA (bit 18) supported (AMX can manage TILEDATA)
328 0xd, 0, ebx, 31:0, xsave_sz_xcr0_enabled , XSAVE/XRSTR area byte size, for XCR0 enabled features
329 0xd, 0, ecx, 31:0, xsave_sz_max , XSAVE/XRSTR area max byte size, all CPU features
330 0xd, 0, edx, 30, xcr0_lwp , AMD XCR0.LWP (bit 62) supported (Light-weight Profiling)
331 0xd, 1, eax, 0, xsaveopt , XSAVEOPT instruction
332 0xd, 1, eax, 1, xsavec , XSAVEC instruction
333 0xd, 1, eax, 2, xgetbv1 , XGETBV instruction with ECX = 1
334 0xd, 1, eax, 3, xsaves , XSAVES/XRSTORS instructions (and XSS MSR)
335 0xd, 1, eax, 4, xfd , Extended feature disable support
336 0xd, 1, ebx, 31:0, xsave_sz_xcr0_xmms_enabled, XSAVE area size, all XCR0 and XMMS features enabled
337 0xd, 1, ecx, 8, xss_pt , PT state, supported
338 0xd, 1, ecx, 10, xss_pasid , PASID state, supported
339 0xd, 1, ecx, 11, xss_cet_u , CET user state, supported
340 0xd, 1, ecx, 12, xss_cet_p , CET supervisor state, supported
341 0xd, 1, ecx, 13, xss_hdc , HDC state, supported
342 0xd, 1, ecx, 14, xss_uintr , UINTR state, supported
343 0xd, 1, ecx, 15, xss_lbr , LBR state, supported
344 0xd, 1, ecx, 16, xss_hwp , HWP state, supported
345 0xd, 63:2, eax, 31:0, xsave_sz , Size of save area for subleaf-N feature, in bytes
346 0xd, 63:2, ebx, 31:0, xsave_offset , Offset of save area for subleaf-N feature, in bytes
347 0xd, 63:2, ecx, 0, is_xss_bit , Subleaf N describes an XSS bit, otherwise XCR0 bit
348 0xd, 63:2, ecx, 1, compacted_xsave_64byte_aligned, When compacted, subleaf-N feature xsave area is 64-byte aligned
349# Leaf FH
350# Intel RDT / AMD PQoS resource monitoring
351 0xf, 0, ebx, 31:0, core_rmid_max , RMID max, within this core, all types (0-based)
352 0xf, 0, edx, 1, cqm_llc , LLC QoS-monitoring supported
353 0xf, 1, eax, 7:0, l3c_qm_bitwidth , L3 QoS-monitoring counter bitwidth (24-based)
354 0xf, 1, eax, 8, l3c_qm_overflow_bit , QM_CTR MSR bit 61 is an overflow bit
355 0xf, 1, ebx, 31:0, l3c_qm_conver_factor , QM_CTR MSR conversion factor to bytes
356 0xf, 1, ecx, 31:0, l3c_qm_rmid_max , L3 QoS-monitoring max RMID
357 0xf, 1, edx, 0, cqm_occup_llc , L3 QoS occupancy monitoring supported
358 0xf, 1, edx, 1, cqm_mbm_total , L3 QoS total bandwidth monitoring supported
359 0xf, 1, edx, 2, cqm_mbm_local , L3 QoS local bandwidth monitoring supported
360# Leaf 10H
361# Intel RDT / AMD PQoS allocation enumeration
362 0x10, 0, ebx, 1, cat_l3 , L3 Cache Allocation Technology supported
363 0x10, 0, ebx, 2, cat_l2 , L2 Cache Allocation Technology supported
364 0x10, 0, ebx, 3, mba , Memory Bandwidth Allocation supported
365 0x10, 2:1, eax, 4:0, cat_cbm_len , L3/L2_CAT capacity bitmask length, minus-one notation
366 0x10, 2:1, ebx, 31:0, cat_units_bitmap , L3/L2_CAT bitmap of allocation units
367 0x10, 2:1, ecx, 1, l3_cat_cos_infreq_updates, L3_CAT COS updates should be infrequent
368 0x10, 2:1, ecx, 2, cdp_l3 , L3/L2_CAT CDP (Code and Data Prioritization)
369 0x10, 2:1, ecx, 3, cat_sparse_1s , L3/L2_CAT non-contiguous 1s value supported
370 0x10, 2:1, edx, 15:0, cat_cos_max , L3/L2_CAT max COS (Class of Service) supported
371 0x10, 3, eax, 11:0, mba_max_delay , Max MBA throttling value; minus-one notation
372 0x10, 3, ecx, 0, per_thread_mba , Per-thread MBA controls are supported
373 0x10, 3, ecx, 2, mba_delay_linear , Delay values are linear
374 0x10, 3, edx, 15:0, mba_cos_max , MBA max Class of Service supported
375# Leaf 12H
376# Intel Software Guard Extensions (SGX) enumeration
377 0x12, 0, eax, 0, sgx1 , SGX1 leaf functions supported
378 0x12, 0, eax, 1, sgx2 , SGX2 leaf functions supported
379 0x12, 0, eax, 5, enclv_leaves , ENCLV leaves (E{INC,DEC}VIRTCHILD, ESETCONTEXT) supported
380 0x12, 0, eax, 6, encls_leaves , ENCLS leaves (ENCLS ETRACKC, ERDINFO, ELDBC, ELDUC) supported
381 0x12, 0, eax, 7, enclu_everifyreport2 , ENCLU leaf EVERIFYREPORT2 supported
382 0x12, 0, eax, 10, encls_eupdatesvn , ENCLS leaf EUPDATESVN supported
383 0x12, 0, eax, 11, sgx_edeccssa , ENCLU leaf EDECCSSA supported
384 0x12, 0, ebx, 0, miscselect_exinfo , SSA.MISC frame: reporting #PF and #GP exceptions inside enclave supported
385 0x12, 0, ebx, 1, miscselect_cpinfo , SSA.MISC frame: reporting #CP exceptions inside enclave supported
386 0x12, 0, edx, 7:0, max_enclave_sz_not64 , Maximum enclave size in non-64-bit mode (log2)
387 0x12, 0, edx, 15:8, max_enclave_sz_64 , Maximum enclave size in 64-bit mode (log2)
388 0x12, 1, eax, 0, secs_attr_init , ATTRIBUTES.INIT supported (enclave initialized by EINIT)
389 0x12, 1, eax, 1, secs_attr_debug , ATTRIBUTES.DEBUG supported (enclave permits debugger read/write)
390 0x12, 1, eax, 2, secs_attr_mode64bit , ATTRIBUTES.MODE64BIT supported (enclave runs in 64-bit mode)
391 0x12, 1, eax, 4, secs_attr_provisionkey , ATTRIBUTES.PROVISIONKEY supported (provisioning key available)
392 0x12, 1, eax, 5, secs_attr_einittoken_key, ATTRIBUTES.EINITTOKEN_KEY supported (EINIT token key available)
393 0x12, 1, eax, 6, secs_attr_cet , ATTRIBUTES.CET supported (enable CET attributes)
394 0x12, 1, eax, 7, secs_attr_kss , ATTRIBUTES.KSS supported (Key Separation and Sharing enabled)
395 0x12, 1, eax, 10, secs_attr_aexnotify , ATTRIBUTES.AEXNOTIFY supported (enclave threads may get AEX notifications
396 0x12, 1, ecx, 0, xfrm_x87 , Enclave XFRM.X87 (bit 0) supported
397 0x12, 1, ecx, 1, xfrm_sse , Enclave XFRM.SEE (bit 1) supported
398 0x12, 1, ecx, 2, xfrm_avx , Enclave XFRM.AVX (bit 2) supported
399 0x12, 1, ecx, 3, xfrm_mpx_bndregs , Enclave XFRM.BNDREGS (bit 3) supported (MPX BND0-BND3 regs)
400 0x12, 1, ecx, 4, xfrm_mpx_bndcsr , Enclave XFRM.BNDCSR (bit 4) supported (MPX BNDCFGU/BNDSTATUS regs)
401 0x12, 1, ecx, 5, xfrm_avx512_opmask , Enclave XFRM.OPMASK (bit 5) supported (AVX-512 k0-k7 regs)
402 0x12, 1, ecx, 6, xfrm_avx512_zmm_hi256 , Enclave XFRM.ZMM_Hi256 (bit 6) supported (AVX-512 ZMM0->ZMM7/15 regs)
403 0x12, 1, ecx, 7, xfrm_avx512_hi16_zmm , Enclave XFRM.HI16_ZMM (bit 7) supported (AVX-512 ZMM16->ZMM31 regs)
404 0x12, 1, ecx, 9, xfrm_pkru , Enclave XFRM.PKRU (bit 9) supported (XSAVE PKRU reg)
405 0x12, 1, ecx, 17, xfrm_tileconfig , Enclave XFRM.TILECONFIG (bit 17) supported (AMX can manage TILECONFIG)
406 0x12, 1, ecx, 18, xfrm_tiledata , Enclave XFRM.TILEDATA (bit 18) supported (AMX can manage TILEDATA)
407 0x12, 31:2, eax, 3:0, subleaf_type , Subleaf type (dictates output layout)
408 0x12, 31:2, eax, 31:12, epc_sec_base_addr_0 , EPC section base addr, bits[12:31]
409 0x12, 31:2, ebx, 19:0, epc_sec_base_addr_1 , EPC section base addr, bits[32:51]
410 0x12, 31:2, ecx, 3:0, epc_sec_type , EPC section type / property encoding
411 0x12, 31:2, ecx, 31:12, epc_sec_size_0 , EPC section size, bits[12:31]
412 0x12, 31:2, edx, 19:0, epc_sec_size_1 , EPC section size, bits[32:51]
413# Leaf 14H
414# Intel Processor Trace enumeration
415 0x14, 0, eax, 31:0, pt_max_subleaf , Max cpuid 0x14 subleaf
416 0x14, 0, ebx, 0, cr3_filtering , IA32_RTIT_CR3_MATCH is accessible
417 0x14, 0, ebx, 1, psb_cyc , Configurable PSB and cycle-accurate mode
418 0x14, 0, ebx, 2, ip_filtering , IP/TraceStop filtering; Warm-reset PT MSRs preservation
419 0x14, 0, ebx, 3, mtc_timing , MTC timing packet; COFI-based packets suppression
420 0x14, 0, ebx, 4, ptwrite , PTWRITE support
421 0x14, 0, ebx, 5, power_event_trace , Power Event Trace support
422 0x14, 0, ebx, 6, psb_pmi_preserve , PSB and PMI preservation support
423 0x14, 0, ebx, 7, event_trace , Event Trace packet generation through IA32_RTIT_CTL.EventEn
424 0x14, 0, ebx, 8, tnt_disable , TNT packet generation disable through IA32_RTIT_CTL.DisTNT
425 0x14, 0, ecx, 0, topa_output , ToPA output scheme support
426 0x14, 0, ecx, 1, topa_multiple_entries , ToPA tables can hold multiple entries
427 0x14, 0, ecx, 2, single_range_output , Single-range output scheme supported
428 0x14, 0, ecx, 3, trance_transport_output, Trace Transport subsystem output support
429 0x14, 0, ecx, 31, ip_payloads_lip , IP payloads have LIP values (CS base included)
430 0x14, 1, eax, 2:0, num_address_ranges , Filtering number of configurable Address Ranges
431 0x14, 1, eax, 31:16, mtc_periods_bmp , Bitmap of supported MTC period encodings
432 0x14, 1, ebx, 15:0, cycle_thresholds_bmp , Bitmap of supported Cycle Threshold encodings
433 0x14, 1, ebx, 31:16, psb_periods_bmp , Bitmap of supported Configurable PSB frequency encodings
434# Leaf 15H
435# Intel TSC (Time Stamp Counter) enumeration
436 0x15, 0, eax, 31:0, tsc_denominator , Denominator of the TSC/'core crystal clock' ratio
437 0x15, 0, ebx, 31:0, tsc_numerator , Numerator of the TSC/'core crystal clock' ratio
438 0x15, 0, ecx, 31:0, cpu_crystal_hz , Core crystal clock nominal frequency, in Hz
439# Leaf 16H
440# Intel processor fequency enumeration
441 0x16, 0, eax, 15:0, cpu_base_mhz , Processor base frequency, in MHz
442 0x16, 0, ebx, 15:0, cpu_max_mhz , Processor max frequency, in MHz
443 0x16, 0, ecx, 15:0, bus_mhz , Bus reference frequency, in MHz
444# Leaf 17H
445# Intel SoC vendor attributes enumeration
446 0x17, 0, eax, 31:0, soc_max_subleaf , Max cpuid leaf 0x17 subleaf
447 0x17, 0, ebx, 15:0, soc_vendor_id , SoC vendor ID
448 0x17, 0, ebx, 16, is_vendor_scheme , Assigned by industry enumaeratoion scheme (not Intel)
449 0x17, 0, ecx, 31:0, soc_proj_id , SoC project ID, assigned by vendor
450 0x17, 0, edx, 31:0, soc_stepping_id , Soc project stepping ID, assigned by vendor
451 0x17, 3:1, eax, 31:0, vendor_brand_a , Vendor Brand ID string, bytes subleaf_nr * (0 -> 3)
452 0x17, 3:1, ebx, 31:0, vendor_brand_b , Vendor Brand ID string, bytes subleaf_nr * (4 -> 7)
453 0x17, 3:1, ecx, 31:0, vendor_brand_c , Vendor Brand ID string, bytes subleaf_nr * (8 -> 11)
454 0x17, 3:1, edx, 31:0, vendor_brand_d , Vendor Brand ID string, bytes subleaf_nr * (12 -> 15)
455# Leaf 18H
456# Intel determenestic address translation (TLB) parameters
457 0x18, 31:0, eax, 31:0, tlb_max_subleaf , Max cpuid 0x18 subleaf
458 0x18, 31:0, ebx, 0, tlb_4k_page , TLB 4KB-page entries supported
459 0x18, 31:0, ebx, 1, tlb_2m_page , TLB 2MB-page entries supported
460 0x18, 31:0, ebx, 2, tlb_4m_page , TLB 4MB-page entries supported
461 0x18, 31:0, ebx, 3, tlb_1g_page , TLB 1GB-page entries supported
462 0x18, 31:0, ebx, 10:8, hard_partitioning , (Hard/Soft) partitioning between logical CPUs sharing this struct
463 0x18, 31:0, ebx, 31:16, n_way_associative , Ways of associativity
464 0x18, 31:0, ecx, 31:0, n_sets , Number of sets
465 0x18, 31:0, edx, 4:0, tlb_type , Translation cache type (TLB type)
466 0x18, 31:0, edx, 7:5, tlb_cache_level , Translation cache level (1-based)
467 0x18, 31:0, edx, 8, is_fully_associative , Fully-associative structure
468 0x18, 31:0, edx, 25:14, tlb_max_addressible_ids, Max num of addressible IDs for logical CPUs sharing this TLB - 1
469# Leaf 19H
470# Intel Key Locker enumeration
471 0x19, 0, eax, 0, kl_cpl0_only , CPL0-only key Locker restriction supported
472 0x19, 0, eax, 1, kl_no_encrypt , No-encrypt key locker restriction supported
473 0x19, 0, eax, 2, kl_no_decrypt , No-decrypt key locker restriction supported
474 0x19, 0, ebx, 0, aes_keylocker , AES key locker instructions supported
475 0x19, 0, ebx, 2, aes_keylocker_wide , AES wide key locker instructions supported
476 0x19, 0, ebx, 4, kl_msr_iwkey , Key locker MSRs and IWKEY backups supported
477 0x19, 0, ecx, 0, loadiwkey_no_backup , LOADIWKEY NoBackup parameter supported
478 0x19, 0, ecx, 1, iwkey_rand , IWKEY randomization (KeySource encoding 1) supported
479# Leaf 1AH
480# Intel hybrid CPUs identification (e.g. Atom, Core)
481 0x1a, 0, eax, 23:0, core_native_model , This core's native model ID
482 0x1a, 0, eax, 31:24, core_type , This core's type
483# Leaf 1BH
484# Intel PCONFIG (Platform configuration) enumeration
485 0x1b, 31:0, eax, 11:0, pconfig_subleaf_type , CPUID 0x1b subleaf type
486 0x1b, 31:0, ebx, 31:0, pconfig_target_id_x , A supported PCONFIG target ID
487 0x1b, 31:0, ecx, 31:0, pconfig_target_id_y , A supported PCONFIG target ID
488 0x1b, 31:0, edx, 31:0, pconfig_target_id_z , A supported PCONFIG target ID
489# Leaf 1CH
490# Intel LBR (Last Branch Record) enumeration
491 0x1c, 0, eax, 0, lbr_depth_8 , Max stack depth (number of LBR entries) = 8
492 0x1c, 0, eax, 1, lbr_depth_16 , Max stack depth (number of LBR entries) = 16
493 0x1c, 0, eax, 2, lbr_depth_24 , Max stack depth (number of LBR entries) = 24
494 0x1c, 0, eax, 3, lbr_depth_32 , Max stack depth (number of LBR entries) = 32
495 0x1c, 0, eax, 4, lbr_depth_40 , Max stack depth (number of LBR entries) = 40
496 0x1c, 0, eax, 5, lbr_depth_48 , Max stack depth (number of LBR entries) = 48
497 0x1c, 0, eax, 6, lbr_depth_56 , Max stack depth (number of LBR entries) = 56
498 0x1c, 0, eax, 7, lbr_depth_64 , Max stack depth (number of LBR entries) = 64
499 0x1c, 0, eax, 30, lbr_deep_c_reset , LBRs maybe cleared on MWAIT C-state > C1
500 0x1c, 0, eax, 31, lbr_ip_is_lip , LBR IP contain Last IP, otherwise effective IP
501 0x1c, 0, ebx, 0, lbr_cpl , CPL filtering (non-zero IA32_LBR_CTL[2:1]) supported
502 0x1c, 0, ebx, 1, lbr_branch_filter , Branch filtering (non-zero IA32_LBR_CTL[22:16]) supported
503 0x1c, 0, ebx, 2, lbr_call_stack , Call-stack mode (IA32_LBR_CTL[3] = 1) supported
504 0x1c, 0, ecx, 0, lbr_mispredict , Branch misprediction bit supported (IA32_LBR_x_INFO[63])
505 0x1c, 0, ecx, 1, lbr_timed_lbr , Timed LBRs (CPU cycles since last LBR entry) supported
506 0x1c, 0, ecx, 2, lbr_branch_type , Branch type field (IA32_LBR_INFO_x[59:56]) supported
507 0x1c, 0, ecx, 19:16, lbr_events_gpc_bmp , LBR PMU-events logging support; bitmap for first 4 GP (general-purpose) Counters
508# Leaf 1DH
509# Intel AMX (Advanced Matrix Extensions) tile information
510 0x1d, 0, eax, 31:0, amx_max_palette , Highest palette ID / subleaf ID
511 0x1d, 1, eax, 15:0, amx_palette_size , AMX palette total tiles size, in bytes
512 0x1d, 1, eax, 31:16, amx_tile_size , AMX single tile's size, in bytes
513 0x1d, 1, ebx, 15:0, amx_tile_row_size , AMX tile single row's size, in bytes
514 0x1d, 1, ebx, 31:16, amx_palette_nr_tiles , AMX palette number of tiles
515 0x1d, 1, ecx, 15:0, amx_tile_nr_rows , AMX tile max number of rows
516# Leaf 1EH
517# Intel AMX, TMUL (Tile-matrix MULtiply) accelerator unit enumeration
518 0x1e, 0, ebx, 7:0, tmul_maxk , TMUL unit maximum height, K (rows or columns)
519 0x1e, 0, ebx, 23:8, tmul_maxn , TMUL unit maxiumum SIMD dimension, N (column bytes)
520# Leaf 1FH
521# Intel extended topology enumeration v2
522 0x1f, 5:0, eax, 4:0, x2apic_id_shift , Bit width of this level (previous levels inclusive)
523 0x1f, 5:0, ebx, 15:0, domain_lcpus_count , Logical CPUs count across all instances of this domain
524 0x1f, 5:0, ecx, 7:0, domain_level , This domain level (subleaf ID)
525 0x1f, 5:0, ecx, 15:8, domain_type , This domain type
526 0x1f, 5:0, edx, 31:0, x2apic_id , x2APIC ID of current logical CPU
527# Leaf 20H
528# Intel HRESET (History Reset) enumeration
529 0x20, 0, eax, 31:0, hreset_nr_subleaves , CPUID 0x20 max subleaf + 1
530 0x20, 0, ebx, 0, hreset_thread_director , HRESET of Intel thread director is supported
531# Leaf 21H
532# Intel TD (Trust Domain) guest execution environment enumeration
533 0x21, 0, ebx, 31:0, tdx_vendorid_0 , TDX vendor ID string bytes 0 - 3
534 0x21, 0, ecx, 31:0, tdx_vendorid_2 , CPU vendor ID string bytes 8 - 11
535 0x21, 0, edx, 31:0, tdx_vendorid_1 , CPU vendor ID string bytes 4 - 7
536# Leaf 23H
537# Intel Architectural Performance Monitoring Extended (ArchPerfmonExt)
538 0x23, 0, eax, 1, subleaf_1_counters , Subleaf 1, PMU counters bitmaps, is valid
539 0x23, 0, eax, 3, subleaf_3_events , Subleaf 3, PMU events bitmaps, is valid
540 0x23, 0, ebx, 0, unitmask2 , IA32_PERFEVTSELx MSRs UnitMask2 is supported
541 0x23, 0, ebx, 1, zbit , IA32_PERFEVTSELx MSRs Z-bit is supported
542 0x23, 1, eax, 31:0, pmu_gp_counters_bitmap , General-purpose PMU counters bitmap
543 0x23, 1, ebx, 31:0, pmu_f_counters_bitmap , Fixed PMU counters bitmap
544 0x23, 3, eax, 0, core_cycles_evt , Core cycles event supported
545 0x23, 3, eax, 1, insn_retired_evt , Instructions retired event supported
546 0x23, 3, eax, 2, ref_cycles_evt , Reference cycles event supported
547 0x23, 3, eax, 3, llc_refs_evt , Last-level cache references event supported
548 0x23, 3, eax, 4, llc_misses_evt , Last-level cache misses event supported
549 0x23, 3, eax, 5, br_insn_ret_evt , Branch instruction retired event supported
550 0x23, 3, eax, 6, br_mispr_evt , Branch mispredict retired event supported
551 0x23, 3, eax, 7, td_slots_evt , Topdown slots event supported
552 0x23, 3, eax, 8, td_backend_bound_evt , Topdown backend bound event supported
553 0x23, 3, eax, 9, td_bad_spec_evt , Topdown bad speculation event supported
554 0x23, 3, eax, 10, td_frontend_bound_evt , Topdown frontend bound event supported
555 0x23, 3, eax, 11, td_retiring_evt , Topdown retiring event support
556# Leaf 40000000H
557# Maximum hypervisor standard leaf + hypervisor vendor string
5580x40000000, 0, eax, 31:0, max_hyp_leaf , Maximum hypervisor standard leaf number
5590x40000000, 0, ebx, 31:0, hypervisor_id_0 , Hypervisor ID string bytes 0 - 3
5600x40000000, 0, ecx, 31:0, hypervisor_id_1 , Hypervisor ID string bytes 4 - 7
5610x40000000, 0, edx, 31:0, hypervisor_id_2 , Hypervisor ID string bytes 8 - 11
562# Leaf 80000000H
563# Maximum extended leaf number + CPU vendor string (AMD)
5640x80000000, 0, eax, 31:0, max_ext_leaf , Maximum extended cpuid leaf supported
5650x80000000, 0, ebx, 31:0, cpu_vendorid_0 , Vendor ID string bytes 0 - 3
5660x80000000, 0, ecx, 31:0, cpu_vendorid_2 , Vendor ID string bytes 8 - 11
5670x80000000, 0, edx, 31:0, cpu_vendorid_1 , Vendor ID string bytes 4 - 7
568# Leaf 80000001H
569# Extended CPU feature identifiers
5700x80000001, 0, eax, 3:0, e_stepping_id , Stepping ID
5710x80000001, 0, eax, 7:4, e_base_model , Base processor model
5720x80000001, 0, eax, 11:8, e_base_family , Base processor family
5730x80000001, 0, eax, 19:16, e_ext_model , Extended processor model
5740x80000001, 0, eax, 27:20, e_ext_family , Extended processor family
5750x80000001, 0, ebx, 15:0, brand_id , Brand ID
5760x80000001, 0, ebx, 31:28, pkg_type , Package type
5770x80000001, 0, ecx, 0, lahf_lm , LAHF and SAHF in 64-bit mode
5780x80000001, 0, ecx, 1, cmp_legacy , Multi-processing legacy mode (No HT)
5790x80000001, 0, ecx, 2, svm , Secure Virtual Machine
5800x80000001, 0, ecx, 3, extapic , Extended APIC space
5810x80000001, 0, ecx, 4, cr8_legacy , LOCK MOV CR0 means MOV CR8
5820x80000001, 0, ecx, 5, abm , LZCNT advanced bit manipulation
5830x80000001, 0, ecx, 6, sse4a , SSE4A support
5840x80000001, 0, ecx, 7, misalignsse , Misaligned SSE mode
5850x80000001, 0, ecx, 8, 3dnowprefetch , 3DNow PREFETCH/PREFETCHW support
5860x80000001, 0, ecx, 9, osvw , OS visible workaround
5870x80000001, 0, ecx, 10, ibs , Instruction based sampling
5880x80000001, 0, ecx, 11, xop , XOP: extended operation (AVX instructions)
5890x80000001, 0, ecx, 12, skinit , SKINIT/STGI support
5900x80000001, 0, ecx, 13, wdt , Watchdog timer support
5910x80000001, 0, ecx, 15, lwp , Lightweight profiling
5920x80000001, 0, ecx, 16, fma4 , 4-operand FMA instruction
5930x80000001, 0, ecx, 17, tce , Translation cache extension
5940x80000001, 0, ecx, 19, nodeid_msr , NodeId MSR (0xc001100c)
5950x80000001, 0, ecx, 21, tbm , Trailing bit manipulations
5960x80000001, 0, ecx, 22, topoext , Topology Extensions (cpuid leaf 0x8000001d)
5970x80000001, 0, ecx, 23, perfctr_core , Core performance counter extensions
5980x80000001, 0, ecx, 24, perfctr_nb , NB/DF performance counter extensions
5990x80000001, 0, ecx, 26, bpext , Data access breakpoint extension
6000x80000001, 0, ecx, 27, ptsc , Performance time-stamp counter
6010x80000001, 0, ecx, 28, perfctr_llc , LLC (L3) performance counter extensions
6020x80000001, 0, ecx, 29, mwaitx , MWAITX/MONITORX support
6030x80000001, 0, ecx, 30, addr_mask_ext , Breakpoint address mask extension (to bit 31)
6040x80000001, 0, edx, 0, e_fpu , Floating-Point Unit on-chip (x87)
6050x80000001, 0, edx, 1, e_vme , Virtual-8086 Mode Extensions
6060x80000001, 0, edx, 2, e_de , Debugging Extensions
6070x80000001, 0, edx, 3, e_pse , Page Size Extension
6080x80000001, 0, edx, 4, e_tsc , Time Stamp Counter
6090x80000001, 0, edx, 5, e_msr , Model-Specific Registers (RDMSR and WRMSR support)
6100x80000001, 0, edx, 6, pae , Physical Address Extensions
6110x80000001, 0, edx, 7, mce , Machine Check Exception
6120x80000001, 0, edx, 8, cx8 , CMPXCHG8B instruction
6130x80000001, 0, edx, 9, apic , APIC on-chip
6140x80000001, 0, edx, 11, syscall , SYSCALL and SYSRET instructions
6150x80000001, 0, edx, 12, mtrr , Memory Type Range Registers
6160x80000001, 0, edx, 13, pge , Page Global Extensions
6170x80000001, 0, edx, 14, mca , Machine Check Architecture
6180x80000001, 0, edx, 15, cmov , Conditional Move Instruction
6190x80000001, 0, edx, 16, pat , Page Attribute Table
6200x80000001, 0, edx, 17, pse36 , Page Size Extension (36-bit)
6210x80000001, 0, edx, 19, mp , Out-of-spec AMD Multiprocessing bit
6220x80000001, 0, edx, 20, nx , No-execute page protection
6230x80000001, 0, edx, 22, mmxext , AMD MMX extensions
6240x80000001, 0, edx, 24, e_fxsr , FXSAVE and FXRSTOR instructions
6250x80000001, 0, edx, 25, fxsr_opt , FXSAVE and FXRSTOR optimizations
6260x80000001, 0, edx, 26, pdpe1gb , 1-GB large page support
6270x80000001, 0, edx, 27, rdtscp , RDTSCP instruction
6280x80000001, 0, edx, 29, lm , Long mode (x86-64, 64-bit support)
6290x80000001, 0, edx, 30, 3dnowext , AMD 3DNow extensions
6300x80000001, 0, edx, 31, 3dnow , 3DNow instructions
631# Leaf 80000002H
632# CPU brand ID string, bytes 0 - 15
6330x80000002, 0, eax, 31:0, cpu_brandid_0 , CPU brand ID string, bytes 0 - 3
6340x80000002, 0, ebx, 31:0, cpu_brandid_1 , CPU brand ID string, bytes 4 - 7
6350x80000002, 0, ecx, 31:0, cpu_brandid_2 , CPU brand ID string, bytes 8 - 11
6360x80000002, 0, edx, 31:0, cpu_brandid_3 , CPU brand ID string, bytes 12 - 15
637# Leaf 80000003H
638# CPU brand ID string, bytes 16 - 31
6390x80000003, 0, eax, 31:0, cpu_brandid_4 , CPU brand ID string bytes, 16 - 19
6400x80000003, 0, ebx, 31:0, cpu_brandid_5 , CPU brand ID string bytes, 20 - 23
6410x80000003, 0, ecx, 31:0, cpu_brandid_6 , CPU brand ID string bytes, 24 - 27
6420x80000003, 0, edx, 31:0, cpu_brandid_7 , CPU brand ID string bytes, 28 - 31
643# Leaf 80000004H
644# CPU brand ID string, bytes 32 - 47
6450x80000004, 0, eax, 31:0, cpu_brandid_8 , CPU brand ID string, bytes 32 - 35
6460x80000004, 0, ebx, 31:0, cpu_brandid_9 , CPU brand ID string, bytes 36 - 39
6470x80000004, 0, ecx, 31:0, cpu_brandid_10 , CPU brand ID string, bytes 40 - 43
6480x80000004, 0, edx, 31:0, cpu_brandid_11 , CPU brand ID string, bytes 44 - 47
649# Leaf 80000005H
650# AMD L1 cache and L1 TLB enumeration
6510x80000005, 0, eax, 7:0, l1_itlb_2m_4m_nentries , L1 ITLB #entires, 2M and 4M pages
6520x80000005, 0, eax, 15:8, l1_itlb_2m_4m_assoc , L1 ITLB associativity, 2M and 4M pages
6530x80000005, 0, eax, 23:16, l1_dtlb_2m_4m_nentries , L1 DTLB #entires, 2M and 4M pages
6540x80000005, 0, eax, 31:24, l1_dtlb_2m_4m_assoc , L1 DTLB associativity, 2M and 4M pages
6550x80000005, 0, ebx, 7:0, l1_itlb_4k_nentries , L1 ITLB #entries, 4K pages
6560x80000005, 0, ebx, 15:8, l1_itlb_4k_assoc , L1 ITLB associativity, 4K pages
6570x80000005, 0, ebx, 23:16, l1_dtlb_4k_nentries , L1 DTLB #entries, 4K pages
6580x80000005, 0, ebx, 31:24, l1_dtlb_4k_assoc , L1 DTLB associativity, 4K pages
6590x80000005, 0, ecx, 7:0, l1_dcache_line_size , L1 dcache line size, in bytes
6600x80000005, 0, ecx, 15:8, l1_dcache_nlines , L1 dcache lines per tag
6610x80000005, 0, ecx, 23:16, l1_dcache_assoc , L1 dcache associativity
6620x80000005, 0, ecx, 31:24, l1_dcache_size_kb , L1 dcache size, in KB
6630x80000005, 0, edx, 7:0, l1_icache_line_size , L1 icache line size, in bytes
6640x80000005, 0, edx, 15:8, l1_icache_nlines , L1 icache lines per tag
6650x80000005, 0, edx, 23:16, l1_icache_assoc , L1 icache associativity
6660x80000005, 0, edx, 31:24, l1_icache_size_kb , L1 icache size, in KB
667# Leaf 80000006H
668# (Mostly AMD) L2 TLB, L2 cache, and L3 cache enumeration
6690x80000006, 0, eax, 11:0, l2_itlb_2m_4m_nentries , L2 iTLB #entries, 2M and 4M pages
6700x80000006, 0, eax, 15:12, l2_itlb_2m_4m_assoc , L2 iTLB associativity, 2M and 4M pages
6710x80000006, 0, eax, 27:16, l2_dtlb_2m_4m_nentries , L2 dTLB #entries, 2M and 4M pages
6720x80000006, 0, eax, 31:28, l2_dtlb_2m_4m_assoc , L2 dTLB associativity, 2M and 4M pages
6730x80000006, 0, ebx, 11:0, l2_itlb_4k_nentries , L2 iTLB #entries, 4K pages
6740x80000006, 0, ebx, 15:12, l2_itlb_4k_assoc , L2 iTLB associativity, 4K pages
6750x80000006, 0, ebx, 27:16, l2_dtlb_4k_nentries , L2 dTLB #entries, 4K pages
6760x80000006, 0, ebx, 31:28, l2_dtlb_4k_assoc , L2 dTLB associativity, 4K pages
6770x80000006, 0, ecx, 7:0, l2_line_size , L2 cache line size, in bytes
6780x80000006, 0, ecx, 11:8, l2_nlines , L2 cache number of lines per tag
6790x80000006, 0, ecx, 15:12, l2_assoc , L2 cache associativity
6800x80000006, 0, ecx, 31:16, l2_size_kb , L2 cache size, in KB
6810x80000006, 0, edx, 7:0, l3_line_size , L3 cache line size, in bytes
6820x80000006, 0, edx, 11:8, l3_nlines , L3 cache number of lines per tag
6830x80000006, 0, edx, 15:12, l3_assoc , L3 cache associativity
6840x80000006, 0, edx, 31:18, l3_size_range , L3 cache size range
685# Leaf 80000007H
686# CPU power management (mostly AMD) and AMD RAS enumeration
6870x80000007, 0, ebx, 0, overflow_recov , MCA overflow conditions not fatal
6880x80000007, 0, ebx, 1, succor , Software containment of UnCORRectable errors
6890x80000007, 0, ebx, 2, hw_assert , Hardware assert MSRs
6900x80000007, 0, ebx, 3, smca , Scalable MCA (MCAX MSRs)
6910x80000007, 0, ecx, 31:0, cpu_pwr_sample_ratio , CPU power sample time ratio
6920x80000007, 0, edx, 0, digital_temp , Digital temprature sensor
6930x80000007, 0, edx, 1, powernow_freq_id , PowerNOW! frequency scaling
6940x80000007, 0, edx, 2, powernow_volt_id , PowerNOW! voltage scaling
6950x80000007, 0, edx, 3, thermal_trip , THERMTRIP (Thermal Trip)
6960x80000007, 0, edx, 4, hw_thermal_control , Hardware thermal control
6970x80000007, 0, edx, 5, sw_thermal_control , Software thermal control
6980x80000007, 0, edx, 6, 100mhz_steps , 100 MHz multiplier control
6990x80000007, 0, edx, 7, hw_pstate , Hardware P-state control
7000x80000007, 0, edx, 8, constant_tsc , TSC ticks at constant rate across all P and C states
7010x80000007, 0, edx, 9, cpb , Core performance boost
7020x80000007, 0, edx, 10, eff_freq_ro , Read-only effective frequency interface
7030x80000007, 0, edx, 11, proc_feedback , Processor feedback interface (deprecated)
7040x80000007, 0, edx, 12, acc_power , Processor power reporting interface
7050x80000007, 0, edx, 13, connected_standby , CPU Connected Standby support
7060x80000007, 0, edx, 14, rapl , Runtime Average Power Limit interface
707# Leaf 80000008H
708# CPU capacity parameters and extended feature flags (mostly AMD)
7090x80000008, 0, eax, 7:0, phys_addr_bits , Max physical address bits
7100x80000008, 0, eax, 15:8, virt_addr_bits , Max virtual address bits
7110x80000008, 0, eax, 23:16, guest_phys_addr_bits , Max nested-paging guest physical address bits
7120x80000008, 0, ebx, 0, clzero , CLZERO supported
7130x80000008, 0, ebx, 1, irperf , Instruction retired counter MSR
7140x80000008, 0, ebx, 2, xsaveerptr , XSAVE/XRSTOR always saves/restores FPU error pointers
7150x80000008, 0, ebx, 3, invlpgb , INVLPGB broadcasts a TLB invalidate to all threads
7160x80000008, 0, ebx, 4, rdpru , RDPRU (Read Processor Register at User level) supported
7170x80000008, 0, ebx, 6, mba , Memory Bandwidth Allocation (AMD bit)
7180x80000008, 0, ebx, 8, mcommit , MCOMMIT (Memory commit) supported
7190x80000008, 0, ebx, 9, wbnoinvd , WBNOINVD supported
7200x80000008, 0, ebx, 12, amd_ibpb , Indirect Branch Prediction Barrier
7210x80000008, 0, ebx, 13, wbinvd_int , Interruptible WBINVD/WBNOINVD
7220x80000008, 0, ebx, 14, amd_ibrs , Indirect Branch Restricted Speculation
7230x80000008, 0, ebx, 15, amd_stibp , Single Thread Indirect Branch Prediction mode
7240x80000008, 0, ebx, 16, ibrs_always_on , IBRS always-on preferred
7250x80000008, 0, ebx, 17, amd_stibp_always_on , STIBP always-on preferred
7260x80000008, 0, ebx, 18, ibrs_fast , IBRS is preferred over software solution
7270x80000008, 0, ebx, 19, ibrs_same_mode , IBRS provides same mode protection
7280x80000008, 0, ebx, 20, no_efer_lmsle , EFER[LMSLE] bit (Long-Mode Segment Limit Enable) unsupported
7290x80000008, 0, ebx, 21, tlb_flush_nested , INVLPGB RAX[5] bit can be set (nested translations)
7300x80000008, 0, ebx, 23, amd_ppin , Protected Processor Inventory Number
7310x80000008, 0, ebx, 24, amd_ssbd , Speculative Store Bypass Disable
7320x80000008, 0, ebx, 25, virt_ssbd , virtualized SSBD (Speculative Store Bypass Disable)
7330x80000008, 0, ebx, 26, amd_ssb_no , SSBD not needed (fixed in HW)
7340x80000008, 0, ebx, 27, cppc , Collaborative Processor Performance Control
7350x80000008, 0, ebx, 28, amd_psfd , Predictive Store Forward Disable
7360x80000008, 0, ebx, 29, btc_no , CPU not affected by Branch Type Confusion
7370x80000008, 0, ebx, 30, ibpb_ret , IBPB clears RSB/RAS too
7380x80000008, 0, ebx, 31, brs , Branch Sampling supported
7390x80000008, 0, ecx, 7:0, cpu_nthreads , Number of physical threads - 1
7400x80000008, 0, ecx, 15:12, apicid_coreid_len , Number of thread core ID bits (shift) in APIC ID
7410x80000008, 0, ecx, 17:16, perf_tsc_len , Performance time-stamp counter size
7420x80000008, 0, edx, 15:0, invlpgb_max_pages , INVLPGB maximum page count
7430x80000008, 0, edx, 31:16, rdpru_max_reg_id , RDPRU max register ID (ECX input)
744# Leaf 8000000AH
745# AMD SVM (Secure Virtual Machine) enumeration
7460x8000000a, 0, eax, 7:0, svm_version , SVM revision number
7470x8000000a, 0, ebx, 31:0, svm_nasid , Number of address space identifiers (ASID)
7480x8000000a, 0, edx, 0, npt , Nested paging
7490x8000000a, 0, edx, 1, lbrv , LBR virtualization
7500x8000000a, 0, edx, 2, svm_lock , SVM lock
7510x8000000a, 0, edx, 3, nrip_save , NRIP save support on #VMEXIT
7520x8000000a, 0, edx, 4, tsc_scale , MSR based TSC rate control
7530x8000000a, 0, edx, 5, vmcb_clean , VMCB clean bits support
7540x8000000a, 0, edx, 6, flushbyasid , Flush by ASID + Extended VMCB TLB_Control
7550x8000000a, 0, edx, 7, decodeassists , Decode Assists support
7560x8000000a, 0, edx, 10, pausefilter , Pause intercept filter
7570x8000000a, 0, edx, 12, pfthreshold , Pause filter threshold
7580x8000000a, 0, edx, 13, avic , Advanced virtual interrupt controller
7590x8000000a, 0, edx, 15, v_vmsave_vmload , Virtual VMSAVE/VMLOAD (nested virt)
7600x8000000a, 0, edx, 16, vgif , Virtualize the Global Interrupt Flag
7610x8000000a, 0, edx, 17, gmet , Guest mode execution trap
7620x8000000a, 0, edx, 18, x2avic , Virtual x2APIC
7630x8000000a, 0, edx, 19, sss_check , Supervisor Shadow Stack restrictions
7640x8000000a, 0, edx, 20, v_spec_ctrl , Virtual SPEC_CTRL
7650x8000000a, 0, edx, 21, ro_gpt , Read-Only guest page table support
7660x8000000a, 0, edx, 23, h_mce_override , Host MCE override
7670x8000000a, 0, edx, 24, tlbsync_int , TLBSYNC intercept + INVLPGB/TLBSYNC in VMCB
7680x8000000a, 0, edx, 25, vnmi , NMI virtualization
7690x8000000a, 0, edx, 26, ibs_virt , IBS Virtualization
7700x8000000a, 0, edx, 27, ext_lvt_off_chg , Extended LVT offset fault change
7710x8000000a, 0, edx, 28, svme_addr_chk , Guest SVME addr check
772# Leaf 80000019H
773# AMD TLB 1G-pages enumeration
7740x80000019, 0, eax, 11:0, l1_itlb_1g_nentries , L1 iTLB #entries, 1G pages
7750x80000019, 0, eax, 15:12, l1_itlb_1g_assoc , L1 iTLB associativity, 1G pages
7760x80000019, 0, eax, 27:16, l1_dtlb_1g_nentries , L1 dTLB #entries, 1G pages
7770x80000019, 0, eax, 31:28, l1_dtlb_1g_assoc , L1 dTLB associativity, 1G pages
7780x80000019, 0, ebx, 11:0, l2_itlb_1g_nentries , L2 iTLB #entries, 1G pages
7790x80000019, 0, ebx, 15:12, l2_itlb_1g_assoc , L2 iTLB associativity, 1G pages
7800x80000019, 0, ebx, 27:16, l2_dtlb_1g_nentries , L2 dTLB #entries, 1G pages
7810x80000019, 0, ebx, 31:28, l2_dtlb_1g_assoc , L2 dTLB associativity, 1G pages
782# Leaf 8000001AH
783# AMD instruction optimizations enumeration
7840x8000001a, 0, eax, 0, fp_128 , Internal FP/SIMD exec data path is 128-bits wide
7850x8000001a, 0, eax, 1, movu_preferred , SSE: MOVU* better than MOVL*/MOVH*
7860x8000001a, 0, eax, 2, fp_256 , internal FP/SSE exec data path is 256-bits wide
787# Leaf 8000001BH
788# AMD IBS (Instruction-Based Sampling) enumeration
7890x8000001b, 0, eax, 0, ibs_flags_valid , IBS feature flags valid
7900x8000001b, 0, eax, 1, ibs_fetch_sampling , IBS fetch sampling supported
7910x8000001b, 0, eax, 2, ibs_op_sampling , IBS execution sampling supported
7920x8000001b, 0, eax, 3, ibs_rdwr_op_counter , IBS read/write of op counter supported
7930x8000001b, 0, eax, 4, ibs_op_count , IBS OP counting mode supported
7940x8000001b, 0, eax, 5, ibs_branch_target , IBS branch target address reporting supported
7950x8000001b, 0, eax, 6, ibs_op_counters_ext , IBS IbsOpCurCnt/IbsOpMaxCnt extend by 7 bits
7960x8000001b, 0, eax, 7, ibs_rip_invalid_chk , IBS invalid RIP indication supported
7970x8000001b, 0, eax, 8, ibs_op_branch_fuse , IBS fused branch micro-op indication supported
7980x8000001b, 0, eax, 9, ibs_fetch_ctl_ext , IBS Fetch Control Extended MSR (0xc001103c) supported
7990x8000001b, 0, eax, 10, ibs_op_data_4 , IBS op data 4 MSR supported
8000x8000001b, 0, eax, 11, ibs_l3_miss_filter , IBS L3-miss filtering supported (Zen4+)
801# Leaf 8000001CH
802# AMD LWP (Lightweight Profiling)
8030x8000001c, 0, eax, 0, os_lwp_avail , LWP is available to application programs (supported by OS)
8040x8000001c, 0, eax, 1, os_lpwval , LWPVAL instruction (EventId=1) is supported by OS
8050x8000001c, 0, eax, 2, os_lwp_ire , Instructions Retired Event (EventId=2) is supported by OS
8060x8000001c, 0, eax, 3, os_lwp_bre , Branch Retired Event (EventId=3) is supported by OS
8070x8000001c, 0, eax, 4, os_lwp_dme , DCache Miss Event (EventId=4) is supported by OS
8080x8000001c, 0, eax, 5, os_lwp_cnh , CPU Clocks Not Halted event (EventId=5) is supported by OS
8090x8000001c, 0, eax, 6, os_lwp_rnh , CPU Reference clocks Not Halted event (EventId=6) is supported by OS
8100x8000001c, 0, eax, 29, os_lwp_cont , LWP sampling in continuous mode is supported by OS
8110x8000001c, 0, eax, 30, os_lwp_ptsc , Performance Time Stamp Counter in event records is supported by OS
8120x8000001c, 0, eax, 31, os_lwp_int , Interrupt on threshold overflow is supported by OS
8130x8000001c, 0, ebx, 7:0, lwp_lwpcb_sz , LWP Control Block size, in quadwords
8140x8000001c, 0, ebx, 15:8, lwp_event_sz , LWP event record size, in bytes
8150x8000001c, 0, ebx, 23:16, lwp_max_events , LWP max supported EventId value (EventID 255 not included)
8160x8000001c, 0, ebx, 31:24, lwp_event_offset , LWP events area offset in the LWP Control Block
8170x8000001c, 0, ecx, 4:0, lwp_latency_max , Num of bits in cache latency counters (10 to 31)
8180x8000001c, 0, ecx, 5, lwp_data_adddr , Cache miss events report the data address of the reference
8190x8000001c, 0, ecx, 8:6, lwp_latency_rnd , Amount by which cache latency is rounded
8200x8000001c, 0, ecx, 15:9, lwp_version , LWP implementation version
8210x8000001c, 0, ecx, 23:16, lwp_buf_min_sz , LWP event ring buffer min size, in units of 32 event records
8220x8000001c, 0, ecx, 28, lwp_branch_predict , Branches Retired events can be filtered
8230x8000001c, 0, ecx, 29, lwp_ip_filtering , IP filtering (IPI, IPF, BaseIP, and LimitIP @ LWPCP) supported
8240x8000001c, 0, ecx, 30, lwp_cache_levels , Cache-related events can be filtered by cache level
8250x8000001c, 0, ecx, 31, lwp_cache_latency , Cache-related events can be filtered by latency
8260x8000001c, 0, edx, 0, hw_lwp_avail , LWP is available in Hardware
8270x8000001c, 0, edx, 1, hw_lpwval , LWPVAL instruction (EventId=1) is available in HW
8280x8000001c, 0, edx, 2, hw_lwp_ire , Instructions Retired Event (EventId=2) is available in HW
8290x8000001c, 0, edx, 3, hw_lwp_bre , Branch Retired Event (EventId=3) is available in HW
8300x8000001c, 0, edx, 4, hw_lwp_dme , DCache Miss Event (EventId=4) is available in HW
8310x8000001c, 0, edx, 5, hw_lwp_cnh , CPU Clocks Not Halted event (EventId=5) is available in HW
8320x8000001c, 0, edx, 6, hw_lwp_rnh , CPU Reference clocks Not Halted event (EventId=6) is available in HW
8330x8000001c, 0, edx, 29, hw_lwp_cont , LWP sampling in continuous mode is available in HW
8340x8000001c, 0, edx, 30, hw_lwp_ptsc , Performance Time Stamp Counter in event records is available in HW
8350x8000001c, 0, edx, 31, hw_lwp_int , Interrupt on threshold overflow is available in HW
836# Leaf 8000001DH
837# AMD deterministic cache parameters
8380x8000001d, 31:0, eax, 4:0, cache_type , Cache type field
8390x8000001d, 31:0, eax, 7:5, cache_level , Cache level (1-based)
8400x8000001d, 31:0, eax, 8, cache_self_init , Self-initializing cache level
8410x8000001d, 31:0, eax, 9, fully_associative , Fully-associative cache
8420x8000001d, 31:0, eax, 25:14, num_threads_sharing , Number of logical CPUs sharing cache
8430x8000001d, 31:0, ebx, 11:0, cache_linesize , System coherency line size (0-based)
8440x8000001d, 31:0, ebx, 21:12, cache_npartitions , Physical line partitions (0-based)
8450x8000001d, 31:0, ebx, 31:22, cache_nways , Ways of associativity (0-based)
8460x8000001d, 31:0, ecx, 30:0, cache_nsets , Cache number of sets (0-based)
8470x8000001d, 31:0, edx, 0, wbinvd_rll_no_guarantee, WBINVD/INVD not guaranteed for Remote Lower-Level caches
8480x8000001d, 31:0, edx, 1, ll_inclusive , Cache is inclusive of Lower-Level caches
849# Leaf 8000001EH
850# AMD CPU topology enumeration
8510x8000001e, 0, eax, 31:0, ext_apic_id , Extended APIC ID
8520x8000001e, 0, ebx, 7:0, core_id , Unique per-socket logical core unit ID
8530x8000001e, 0, ebx, 15:8, core_nthreas , #Threads per core (zero-based)
8540x8000001e, 0, ecx, 7:0, node_id , Node (die) ID of invoking logical CPU
8550x8000001e, 0, ecx, 10:8, nnodes_per_socket , #nodes in invoking logical CPU's package/socket
856# Leaf 8000001FH
857# AMD encrypted memory capabilities enumeration (SME/SEV)
8580x8000001f, 0, eax, 0, sme , Secure Memory Encryption supported
8590x8000001f, 0, eax, 1, sev , Secure Encrypted Virtualization supported
8600x8000001f, 0, eax, 2, vm_page_flush , VM Page Flush MSR (0xc001011e) available
8610x8000001f, 0, eax, 3, sev_es , SEV Encrypted State supported
8620x8000001f, 0, eax, 4, sev_nested_paging , SEV secure nested paging supported
8630x8000001f, 0, eax, 5, vm_permission_levels , VMPL supported
8640x8000001f, 0, eax, 6, rpmquery , RPMQUERY instruction supported
8650x8000001f, 0, eax, 7, vmpl_sss , VMPL supervisor shadwo stack supported
8660x8000001f, 0, eax, 8, secure_tsc , Secure TSC supported
8670x8000001f, 0, eax, 9, v_tsc_aux , Hardware virtualizes TSC_AUX
8680x8000001f, 0, eax, 10, sme_coherent , HW enforces cache coherency across encryption domains
8690x8000001f, 0, eax, 11, req_64bit_hypervisor , SEV guest mandates 64-bit hypervisor
8700x8000001f, 0, eax, 12, restricted_injection , Restricted Injection supported
8710x8000001f, 0, eax, 13, alternate_injection , Alternate Injection supported
8720x8000001f, 0, eax, 14, debug_swap , SEV-ES: full debug state swap is supported
8730x8000001f, 0, eax, 15, disallow_host_ibs , SEV-ES: Disallowing IBS use by the host is supported
8740x8000001f, 0, eax, 16, virt_transparent_enc , Virtual Transparent Encryption
8750x8000001f, 0, eax, 17, vmgexit_paremeter , VmgexitParameter is supported in SEV_FEATURES
8760x8000001f, 0, eax, 18, virt_tom_msr , Virtual TOM MSR is supported
8770x8000001f, 0, eax, 19, virt_ibs , IBS state virtualization is supported for SEV-ES guests
8780x8000001f, 0, eax, 24, vmsa_reg_protection , VMSA register protection is supported
8790x8000001f, 0, eax, 25, smt_protection , SMT protection is supported
8800x8000001f, 0, eax, 28, svsm_page_msr , SVSM communication page MSR (0xc001f000h) is supported
8810x8000001f, 0, eax, 29, nested_virt_snp_msr , VIRT_RMPUPDATE/VIRT_PSMASH MSRs are supported
8820x8000001f, 0, ebx, 5:0, pte_cbit_pos , PTE bit number used to enable memory encryption
8830x8000001f, 0, ebx, 11:6, phys_addr_reduction_nbits, Reduction of phys address space when encryption is enabled, in bits
8840x8000001f, 0, ebx, 15:12, vmpl_count , Number of VM permission levels (VMPL) supported
8850x8000001f, 0, ecx, 31:0, enc_guests_max , Max supported number of simultaneous encrypted guests
8860x8000001f, 0, edx, 31:0, min_sev_asid_no_sev_es , Mininum ASID for SEV-enabled SEV-ES-disabled guest
887# Leaf 80000020H
888# AMD Platform QoS extended feature IDs
8890x80000020, 0, ebx, 1, mba , Memory Bandwidth Allocation support
8900x80000020, 0, ebx, 2, smba , Slow Memory Bandwidth Allocation support
8910x80000020, 0, ebx, 3, bmec , Bandwidth Monitoring Event Configuration support
8920x80000020, 0, ebx, 4, l3rr , L3 Range Reservation support
8930x80000020, 1, eax, 31:0, mba_limit_len , MBA enforcement limit size
8940x80000020, 1, edx, 31:0, mba_cos_max , MBA max Class of Service number (zero-based)
8950x80000020, 2, eax, 31:0, smba_limit_len , SMBA enforcement limit size
8960x80000020, 2, edx, 31:0, smba_cos_max , SMBA max Class of Service number (zero-based)
8970x80000020, 3, ebx, 7:0, bmec_num_events , BMEC number of bandwidth events available
8980x80000020, 3, ecx, 0, bmec_local_reads , Local NUMA reads can be tracked
8990x80000020, 3, ecx, 1, bmec_remote_reads , Remote NUMA reads can be tracked
9000x80000020, 3, ecx, 2, bmec_local_nontemp_wr , Local NUMA non-temporal writes can be tracked
9010x80000020, 3, ecx, 3, bmec_remote_nontemp_wr , Remote NUMA non-temporal writes can be tracked
9020x80000020, 3, ecx, 4, bmec_local_slow_mem_rd , Local NUMA slow-memory reads can be tracked
9030x80000020, 3, ecx, 5, bmec_remote_slow_mem_rd, Remote NUMA slow-memory reads can be tracked
9040x80000020, 3, ecx, 6, bmec_all_dirty_victims , Dirty QoS victims to all types of memory can be tracked
905# Leaf 80000021H
906# AMD extended features enumeration 2
9070x80000021, 0, eax, 0, no_nested_data_bp , No nested data breakpoints
9080x80000021, 0, eax, 1, fsgs_non_serializing , WRMSR to {FS,GS,KERNEL_GS}_BASE is non-serializing
9090x80000021, 0, eax, 2, lfence_rdtsc , LFENCE always serializing / synchronizes RDTSC
9100x80000021, 0, eax, 3, smm_page_cfg_lock , SMM paging configuration lock is supported
9110x80000021, 0, eax, 6, null_sel_clr_base , Null selector clears base
9120x80000021, 0, eax, 7, upper_addr_ignore , EFER MSR Upper Address Ignore Enable bit supported
9130x80000021, 0, eax, 8, autoibrs , EFER MSR Automatic IBRS enable bit supported
9140x80000021, 0, eax, 9, no_smm_ctl_msr , SMM_CTL MSR (0xc0010116) is not present
9150x80000021, 0, eax, 10, fsrs_supported , Fast Short Rep Stosb (FSRS) is supported
9160x80000021, 0, eax, 11, fsrc_supported , Fast Short Repe Cmpsb (FSRC) is supported
9170x80000021, 0, eax, 13, prefetch_ctl_msr , Prefetch control MSR is supported
9180x80000021, 0, eax, 17, user_cpuid_disable , #GP when executing CPUID at CPL > 0 is supported
9190x80000021, 0, eax, 18, epsf_supported , Enhanced Predictive Store Forwarding (EPSF) is supported
9200x80000021, 0, ebx, 11:0, microcode_patch_size , Size of microcode patch, in 16-byte units
921# Leaf 80000022H
922# AMD Performance Monitoring v2 enumeration
9230x80000022, 0, eax, 0, perfmon_v2 , Performance monitoring v2 supported
9240x80000022, 0, eax, 1, lbr_v2 , Last Branch Record v2 extensions (LBR Stack)
9250x80000022, 0, eax, 2, lbr_pmc_freeze , Freezing core performance counters / LBR Stack supported
9260x80000022, 0, ebx, 3:0, n_pmc_core , Number of core perfomance counters
9270x80000022, 0, ebx, 9:4, lbr_v2_stack_size , Number of available LBR stack entries
9280x80000022, 0, ebx, 15:10, n_pmc_northbridge , Number of available northbridge (data fabric) performance counters
9290x80000022, 0, ebx, 21:16, n_pmc_umc , Number of available UMC performance counters
9300x80000022, 0, ecx, 31:0, active_umc_bitmask , Active UMCs bitmask
931# Leaf 80000023H
932# AMD Secure Multi-key Encryption enumeration
9330x80000023, 0, eax, 0, mem_hmk_mode , MEM-HMK encryption mode is supported
9340x80000023, 0, ebx, 15:0, mem_hmk_avail_keys , MEM-HMK mode: total num of available encryption keys
935# Leaf 80000026H
936# AMD extended topology enumeration v2
9370x80000026, 3:0, eax, 4:0, x2apic_id_shift , Bit width of this level (previous levels inclusive)
9380x80000026, 3:0, eax, 29, core_has_pwreff_ranking, This core has a power efficiency ranking
9390x80000026, 3:0, eax, 30, domain_has_hybrid_cores, This domain level has hybrid (E, P) cores
9400x80000026, 3:0, eax, 31, domain_core_count_asymm, The 'Core' domain has asymmetric cores count
9410x80000026, 3:0, ebx, 15:0, domain_lcpus_count , Number of logical CPUs at this domain instance
9420x80000026, 3:0, ebx, 23:16, core_pwreff_ranking , This core's static power efficiency ranking
9430x80000026, 3:0, ebx, 27:24, core_native_model_id , This core's native model ID
9440x80000026, 3:0, ebx, 31:28, core_type , This core's type
9450x80000026, 3:0, ecx, 7:0, domain_level , This domain level (subleaf ID)
9460x80000026, 3:0, ecx, 15:8, domain_type , This domain type
9470x80000026, 3:0, edx, 31:0, x2apic_id , x2APIC ID of current logical CPU