339 lines
8.0 KiB
C
339 lines
8.0 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* AMD HSMP Platform Driver
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* Copyright (c) 2024, AMD.
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* All Rights Reserved.
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*
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* This file provides platform device implementations.
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <asm/amd_hsmp.h>
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#include <asm/amd_nb.h>
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#include <linux/device.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include <linux/sysfs.h>
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#include "hsmp.h"
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#define DRIVER_NAME "amd_hsmp"
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#define DRIVER_VERSION "2.3"
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/*
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* To access specific HSMP mailbox register, s/w writes the SMN address of HSMP mailbox
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* register into the SMN_INDEX register, and reads/writes the SMN_DATA reg.
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* Below are required SMN address for HSMP Mailbox register offsets in SMU address space
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*/
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#define SMN_HSMP_BASE 0x3B00000
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#define SMN_HSMP_MSG_ID 0x0010534
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#define SMN_HSMP_MSG_ID_F1A_M0H 0x0010934
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#define SMN_HSMP_MSG_RESP 0x0010980
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#define SMN_HSMP_MSG_DATA 0x00109E0
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#define HSMP_INDEX_REG 0xc4
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#define HSMP_DATA_REG 0xc8
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static struct hsmp_plat_device *hsmp_pdev;
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static int amd_hsmp_pci_rdwr(struct hsmp_socket *sock, u32 offset,
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u32 *value, bool write)
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{
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int ret;
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if (!sock->root)
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return -ENODEV;
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ret = pci_write_config_dword(sock->root, HSMP_INDEX_REG,
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sock->mbinfo.base_addr + offset);
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if (ret)
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return ret;
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ret = (write ? pci_write_config_dword(sock->root, HSMP_DATA_REG, *value)
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: pci_read_config_dword(sock->root, HSMP_DATA_REG, value));
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return ret;
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}
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static ssize_t hsmp_metric_tbl_plat_read(struct file *filp, struct kobject *kobj,
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struct bin_attribute *bin_attr, char *buf,
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loff_t off, size_t count)
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{
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struct hsmp_socket *sock;
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u16 sock_ind;
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sock_ind = (uintptr_t)bin_attr->private;
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if (sock_ind >= hsmp_pdev->num_sockets)
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return -EINVAL;
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sock = &hsmp_pdev->sock[sock_ind];
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return hsmp_metric_tbl_read(sock, buf, count);
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}
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static umode_t hsmp_is_sock_attr_visible(struct kobject *kobj,
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const struct bin_attribute *battr, int id)
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{
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u16 sock_ind;
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sock_ind = (uintptr_t)battr->private;
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if (id == 0 && sock_ind >= hsmp_pdev->num_sockets)
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return SYSFS_GROUP_INVISIBLE;
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if (hsmp_pdev->proto_ver == HSMP_PROTO_VER6)
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return battr->attr.mode;
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return 0;
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}
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/*
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* AMD supports maximum of 8 sockets in a system.
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* Static array of 8 + 1(for NULL) elements is created below
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* to create sysfs groups for sockets.
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* is_bin_visible function is used to show / hide the necessary groups.
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*/
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#define HSMP_BIN_ATTR(index, _list) \
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static struct bin_attribute attr##index = { \
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.attr = { .name = HSMP_METRICS_TABLE_NAME, .mode = 0444}, \
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.private = (void *)index, \
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.read = hsmp_metric_tbl_plat_read, \
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.size = sizeof(struct hsmp_metric_table), \
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}; \
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static struct bin_attribute _list[] = { \
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&attr##index, \
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NULL \
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}
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HSMP_BIN_ATTR(0, *sock0_attr_list);
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HSMP_BIN_ATTR(1, *sock1_attr_list);
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HSMP_BIN_ATTR(2, *sock2_attr_list);
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HSMP_BIN_ATTR(3, *sock3_attr_list);
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HSMP_BIN_ATTR(4, *sock4_attr_list);
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HSMP_BIN_ATTR(5, *sock5_attr_list);
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HSMP_BIN_ATTR(6, *sock6_attr_list);
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HSMP_BIN_ATTR(7, *sock7_attr_list);
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#define HSMP_BIN_ATTR_GRP(index, _list, _name) \
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static struct attribute_group sock##index##_attr_grp = { \
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.bin_attrs = _list, \
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.is_bin_visible = hsmp_is_sock_attr_visible, \
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.name = #_name, \
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}
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HSMP_BIN_ATTR_GRP(0, sock0_attr_list, socket0);
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HSMP_BIN_ATTR_GRP(1, sock1_attr_list, socket1);
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HSMP_BIN_ATTR_GRP(2, sock2_attr_list, socket2);
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HSMP_BIN_ATTR_GRP(3, sock3_attr_list, socket3);
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HSMP_BIN_ATTR_GRP(4, sock4_attr_list, socket4);
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HSMP_BIN_ATTR_GRP(5, sock5_attr_list, socket5);
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HSMP_BIN_ATTR_GRP(6, sock6_attr_list, socket6);
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HSMP_BIN_ATTR_GRP(7, sock7_attr_list, socket7);
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static const struct attribute_group *hsmp_groups[] = {
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&sock0_attr_grp,
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&sock1_attr_grp,
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&sock2_attr_grp,
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&sock3_attr_grp,
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&sock4_attr_grp,
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&sock5_attr_grp,
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&sock6_attr_grp,
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&sock7_attr_grp,
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NULL
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};
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static inline bool is_f1a_m0h(void)
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{
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if (boot_cpu_data.x86 == 0x1A && boot_cpu_data.x86_model <= 0x0F)
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return true;
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return false;
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}
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static int init_platform_device(struct device *dev)
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{
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struct hsmp_socket *sock;
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int ret, i;
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for (i = 0; i < hsmp_pdev->num_sockets; i++) {
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if (!node_to_amd_nb(i))
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return -ENODEV;
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sock = &hsmp_pdev->sock[i];
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sock->root = node_to_amd_nb(i)->root;
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sock->sock_ind = i;
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sock->dev = dev;
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sock->mbinfo.base_addr = SMN_HSMP_BASE;
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sock->amd_hsmp_rdwr = amd_hsmp_pci_rdwr;
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/*
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* This is a transitional change from non-ACPI to ACPI, only
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* family 0x1A, model 0x00 platform is supported for both ACPI and non-ACPI.
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*/
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if (is_f1a_m0h())
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sock->mbinfo.msg_id_off = SMN_HSMP_MSG_ID_F1A_M0H;
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else
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sock->mbinfo.msg_id_off = SMN_HSMP_MSG_ID;
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sock->mbinfo.msg_resp_off = SMN_HSMP_MSG_RESP;
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sock->mbinfo.msg_arg_off = SMN_HSMP_MSG_DATA;
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sema_init(&sock->hsmp_sem, 1);
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/* Test the hsmp interface on each socket */
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ret = hsmp_test(i, 0xDEADBEEF);
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if (ret) {
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dev_err(dev, "HSMP test message failed on Fam:%x model:%x\n",
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boot_cpu_data.x86, boot_cpu_data.x86_model);
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dev_err(dev, "Is HSMP disabled in BIOS ?\n");
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return ret;
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}
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ret = hsmp_cache_proto_ver(i);
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if (ret) {
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dev_err(dev, "Failed to read HSMP protocol version\n");
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return ret;
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}
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if (hsmp_pdev->proto_ver == HSMP_PROTO_VER6) {
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ret = hsmp_get_tbl_dram_base(i);
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if (ret)
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dev_err(dev, "Failed to init metric table\n");
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}
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}
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return 0;
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}
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static int hsmp_pltdrv_probe(struct platform_device *pdev)
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{
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int ret;
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hsmp_pdev->sock = devm_kcalloc(&pdev->dev, hsmp_pdev->num_sockets,
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sizeof(*hsmp_pdev->sock),
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GFP_KERNEL);
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if (!hsmp_pdev->sock)
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return -ENOMEM;
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ret = init_platform_device(&pdev->dev);
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if (ret) {
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dev_err(&pdev->dev, "Failed to init HSMP mailbox\n");
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return ret;
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}
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return hsmp_misc_register(&pdev->dev);
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}
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static void hsmp_pltdrv_remove(struct platform_device *pdev)
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{
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hsmp_misc_deregister();
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}
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static struct platform_driver amd_hsmp_driver = {
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.probe = hsmp_pltdrv_probe,
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.remove = hsmp_pltdrv_remove,
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.driver = {
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.name = DRIVER_NAME,
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.dev_groups = hsmp_groups,
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},
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};
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static struct platform_device *amd_hsmp_platdev;
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static int hsmp_plat_dev_register(void)
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{
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int ret;
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amd_hsmp_platdev = platform_device_alloc(DRIVER_NAME, PLATFORM_DEVID_NONE);
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if (!amd_hsmp_platdev)
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return -ENOMEM;
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ret = platform_device_add(amd_hsmp_platdev);
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if (ret)
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platform_device_put(amd_hsmp_platdev);
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return ret;
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}
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/*
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* This check is only needed for backward compatibility of previous platforms.
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* All new platforms are expected to support ACPI based probing.
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*/
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static bool legacy_hsmp_support(void)
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{
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if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
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return false;
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switch (boot_cpu_data.x86) {
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case 0x19:
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switch (boot_cpu_data.x86_model) {
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case 0x00 ... 0x1F:
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case 0x30 ... 0x3F:
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case 0x90 ... 0x9F:
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case 0xA0 ... 0xAF:
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return true;
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default:
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return false;
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}
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case 0x1A:
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switch (boot_cpu_data.x86_model) {
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case 0x00 ... 0x1F:
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return true;
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default:
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return false;
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}
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default:
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return false;
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}
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return false;
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}
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static int __init hsmp_plt_init(void)
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{
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int ret = -ENODEV;
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if (!legacy_hsmp_support()) {
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pr_info("HSMP is not supported on Family:%x model:%x\n",
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boot_cpu_data.x86, boot_cpu_data.x86_model);
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return ret;
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}
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hsmp_pdev = get_hsmp_pdev();
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if (!hsmp_pdev)
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return -ENOMEM;
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/*
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* amd_nb_num() returns number of SMN/DF interfaces present in the system
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* if we have N SMN/DF interfaces that ideally means N sockets
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*/
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hsmp_pdev->num_sockets = amd_nb_num();
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if (hsmp_pdev->num_sockets == 0 || hsmp_pdev->num_sockets > MAX_AMD_SOCKETS)
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return ret;
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ret = platform_driver_register(&amd_hsmp_driver);
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if (ret)
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return ret;
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ret = hsmp_plat_dev_register();
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if (ret)
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platform_driver_unregister(&amd_hsmp_driver);
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return ret;
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}
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static void __exit hsmp_plt_exit(void)
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{
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platform_device_unregister(amd_hsmp_platdev);
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platform_driver_unregister(&amd_hsmp_driver);
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}
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device_initcall(hsmp_plt_init);
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module_exit(hsmp_plt_exit);
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MODULE_IMPORT_NS("AMD_HSMP");
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MODULE_DESCRIPTION("AMD HSMP Platform Interface Driver");
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MODULE_VERSION(DRIVER_VERSION);
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MODULE_LICENSE("GPL");
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