61 lines
2.1 KiB
Plaintext
61 lines
2.1 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0-only
|
|
#
|
|
# Phy drivers for STMicro platforms
|
|
#
|
|
config PHY_MIPHY28LP
|
|
tristate "STMicroelectronics MIPHY28LP PHY driver for STiH407"
|
|
depends on ARCH_STI
|
|
select GENERIC_PHY
|
|
help
|
|
Enable this to support the miphy transceiver (for SATA/PCIE/USB3)
|
|
that is part of STMicroelectronics STiH407 SoC.
|
|
|
|
config PHY_ST_SPEAR1310_MIPHY
|
|
tristate "ST SPEAR1310-MIPHY driver"
|
|
select GENERIC_PHY
|
|
depends on MACH_SPEAR1310 || COMPILE_TEST
|
|
help
|
|
Support for ST SPEAr1310 MIPHY which can be used for PCIe and SATA.
|
|
|
|
config PHY_ST_SPEAR1340_MIPHY
|
|
tristate "ST SPEAR1340-MIPHY driver"
|
|
select GENERIC_PHY
|
|
depends on MACH_SPEAR1340 || COMPILE_TEST
|
|
help
|
|
Support for ST SPEAr1340 MIPHY which can be used for PCIe and SATA.
|
|
|
|
config PHY_STIH407_USB
|
|
tristate "STMicroelectronics USB2 picoPHY driver for STiH407 family"
|
|
depends on RESET_CONTROLLER
|
|
depends on ARCH_STI || COMPILE_TEST
|
|
select GENERIC_PHY
|
|
help
|
|
Enable this support to enable the picoPHY device used by USB2
|
|
and USB3 controllers on STMicroelectronics STiH407 SoC families.
|
|
|
|
config PHY_STM32_COMBOPHY
|
|
tristate "STMicroelectronics COMBOPHY driver for STM32MP25"
|
|
depends on ARCH_STM32 || COMPILE_TEST
|
|
select GENERIC_PHY
|
|
help
|
|
Enable this to support the COMBOPHY device used by USB3 or PCIe
|
|
controllers on STMicroelectronics STM32MP25 SoC.
|
|
This driver controls the COMBOPHY block to generate the PCIe 100Mhz
|
|
reference clock from either the external clock generator or HSE
|
|
internal SoC clock source.
|
|
|
|
config PHY_STM32_USBPHYC
|
|
tristate "STMicroelectronics STM32 USB HS PHY Controller driver"
|
|
depends on ARCH_STM32 || COMPILE_TEST
|
|
depends on COMMON_CLK
|
|
select GENERIC_PHY
|
|
help
|
|
Enable this to support the High-Speed USB transceivers that are part
|
|
of some STMicroelectronics STM32 SoCs.
|
|
|
|
This driver controls the entire USB PHY block: the USB PHY controller
|
|
(USBPHYC) and the two 8-bit wide UTMI+ interfaces. First interface is
|
|
used by an HS USB Host controller, and the second one is shared
|
|
between an HS USB OTG controller and an HS USB Host controller,
|
|
selected by a USB switch.
|