207 lines
5.5 KiB
C
207 lines
5.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright (C) 2013--2024 Intel Corporation */
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#ifndef IPU6_ISYS_H
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#define IPU6_ISYS_H
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#include <linux/irqreturn.h>
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#include <linux/list.h>
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#include <linux/mutex.h>
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#include <linux/pm_qos.h>
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#include <linux/spinlock_types.h>
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#include <linux/types.h>
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#include <media/media-device.h>
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#include <media/v4l2-async.h>
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#include <media/v4l2-device.h>
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#include "ipu6.h"
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#include "ipu6-fw-isys.h"
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#include "ipu6-isys-csi2.h"
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#include "ipu6-isys-video.h"
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struct ipu6_bus_device;
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#define IPU6_ISYS_ENTITY_PREFIX "Intel IPU6"
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/* FW support max 16 streams */
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#define IPU6_ISYS_MAX_STREAMS 16
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#define ISYS_UNISPART_IRQS (IPU6_ISYS_UNISPART_IRQ_SW | \
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IPU6_ISYS_UNISPART_IRQ_CSI0 | \
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IPU6_ISYS_UNISPART_IRQ_CSI1)
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#define IPU6_ISYS_2600_MEM_LINE_ALIGN 64
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/*
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* Current message queue configuration. These must be big enough
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* so that they never gets full. Queues are located in system memory
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*/
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#define IPU6_ISYS_SIZE_RECV_QUEUE 40
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#define IPU6_ISYS_SIZE_SEND_QUEUE 40
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#define IPU6_ISYS_SIZE_PROXY_RECV_QUEUE 5
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#define IPU6_ISYS_SIZE_PROXY_SEND_QUEUE 5
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#define IPU6_ISYS_NUM_RECV_QUEUE 1
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#define IPU6_ISYS_MIN_WIDTH 2U
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#define IPU6_ISYS_MIN_HEIGHT 2U
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#define IPU6_ISYS_MAX_WIDTH 4672U
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#define IPU6_ISYS_MAX_HEIGHT 3416U
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/* the threshold granularity is 2KB on IPU6 */
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#define IPU6_SRAM_GRANULARITY_SHIFT 11
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#define IPU6_SRAM_GRANULARITY_SIZE 2048
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/* the threshold granularity is 1KB on IPU6SE */
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#define IPU6SE_SRAM_GRANULARITY_SHIFT 10
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#define IPU6SE_SRAM_GRANULARITY_SIZE 1024
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/* IS pixel buffer is 256KB, MaxSRAMSize is 200KB on IPU6 */
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#define IPU6_MAX_SRAM_SIZE (200 << 10)
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/* IS pixel buffer is 128KB, MaxSRAMSize is 96KB on IPU6SE */
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#define IPU6SE_MAX_SRAM_SIZE (96 << 10)
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#define IPU6EP_LTR_VALUE 200
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#define IPU6EP_MIN_MEMOPEN_TH 0x4
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#define IPU6EP_MTL_LTR_VALUE 1023
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#define IPU6EP_MTL_MIN_MEMOPEN_TH 0xc
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struct ltr_did {
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union {
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u32 value;
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struct {
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u8 val0;
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u8 val1;
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u8 val2;
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u8 val3;
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} bits;
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} lut_ltr;
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union {
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u32 value;
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struct {
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u8 th0;
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u8 th1;
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u8 th2;
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u8 th3;
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} bits;
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} lut_fill_time;
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};
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struct isys_iwake_watermark {
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bool iwake_enabled;
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bool force_iwake_disable;
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u32 iwake_threshold;
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u64 isys_pixelbuffer_datarate;
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struct ltr_did ltrdid;
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struct mutex mutex; /* protect whole struct */
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struct ipu6_isys *isys;
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struct list_head video_list;
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};
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struct ipu6_isys_csi2_config {
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u32 nlanes;
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u32 port;
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};
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struct sensor_async_sd {
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struct v4l2_async_connection asc;
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struct ipu6_isys_csi2_config csi2;
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};
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/*
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* struct ipu6_isys
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*
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* @media_dev: Media device
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* @v4l2_dev: V4L2 device
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* @adev: ISYS bus device
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* @power: Is ISYS powered on or not?
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* @isr_bits: Which bits does the ISR handle?
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* @power_lock: Serialise access to power (power state in general)
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* @csi2_rx_ctrl_cached: cached shared value between all CSI2 receivers
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* @streams_lock: serialise access to streams
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* @streams: streams per firmware stream ID
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* @fwcom: fw communication layer private pointer
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* or optional external library private pointer
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* @line_align: line alignment in memory
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* @phy_termcal_val: the termination calibration value, only used for DWC PHY
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* @need_reset: Isys requires d0i0->i3 transition
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* @ref_count: total number of callers fw open
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* @mutex: serialise access isys video open/release related operations
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* @stream_mutex: serialise stream start and stop, queueing requests
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* @pdata: platform data pointer
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* @csi2: CSI-2 receivers
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*/
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struct ipu6_isys {
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struct media_device media_dev;
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struct v4l2_device v4l2_dev;
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struct ipu6_bus_device *adev;
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int power;
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spinlock_t power_lock;
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u32 isr_csi2_bits;
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u32 csi2_rx_ctrl_cached;
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spinlock_t streams_lock;
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struct ipu6_isys_stream streams[IPU6_ISYS_MAX_STREAMS];
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int streams_ref_count[IPU6_ISYS_MAX_STREAMS];
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void *fwcom;
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unsigned int line_align;
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u32 phy_termcal_val;
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bool need_reset;
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bool icache_prefetch;
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bool csi2_cse_ipc_not_supported;
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unsigned int ref_count;
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unsigned int stream_opened;
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unsigned int sensor_type;
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struct mutex mutex;
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struct mutex stream_mutex;
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struct ipu6_isys_pdata *pdata;
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int (*phy_set_power)(struct ipu6_isys *isys,
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struct ipu6_isys_csi2_config *cfg,
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const struct ipu6_isys_csi2_timing *timing,
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bool on);
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struct ipu6_isys_csi2 *csi2;
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struct pm_qos_request pm_qos;
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spinlock_t listlock; /* Protect framebuflist */
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struct list_head framebuflist;
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struct list_head framebuflist_fw;
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struct v4l2_async_notifier notifier;
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struct isys_iwake_watermark iwake_watermark;
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};
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struct isys_fw_msgs {
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union {
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u64 dummy;
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struct ipu6_fw_isys_frame_buff_set_abi frame;
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struct ipu6_fw_isys_stream_cfg_data_abi stream;
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} fw_msg;
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struct list_head head;
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dma_addr_t dma_addr;
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};
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struct isys_fw_msgs *ipu6_get_fw_msg_buf(struct ipu6_isys_stream *stream);
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void ipu6_put_fw_msg_buf(struct ipu6_isys *isys, uintptr_t data);
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void ipu6_cleanup_fw_msg_bufs(struct ipu6_isys *isys);
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extern const struct v4l2_ioctl_ops ipu6_isys_ioctl_ops;
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void isys_setup_hw(struct ipu6_isys *isys);
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irqreturn_t isys_isr(struct ipu6_bus_device *adev);
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void update_watermark_setting(struct ipu6_isys *isys);
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int ipu6_isys_mcd_phy_set_power(struct ipu6_isys *isys,
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struct ipu6_isys_csi2_config *cfg,
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const struct ipu6_isys_csi2_timing *timing,
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bool on);
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int ipu6_isys_dwc_phy_set_power(struct ipu6_isys *isys,
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struct ipu6_isys_csi2_config *cfg,
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const struct ipu6_isys_csi2_timing *timing,
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bool on);
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int ipu6_isys_jsl_phy_set_power(struct ipu6_isys *isys,
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struct ipu6_isys_csi2_config *cfg,
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const struct ipu6_isys_csi2_timing *timing,
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bool on);
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#endif /* IPU6_ISYS_H */
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