424 lines
11 KiB
C
424 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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#include <linux/bits.h>
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#include <linux/i2c.h>
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#include <linux/i2c-mux.h>
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#include <linux/mod_devicetable.h>
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#include <linux/mfd/syscon.h>
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#include <linux/mutex.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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enum rtl9300_bus_freq {
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RTL9300_I2C_STD_FREQ,
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RTL9300_I2C_FAST_FREQ,
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};
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struct rtl9300_i2c;
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struct rtl9300_i2c_chan {
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struct i2c_adapter adap;
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struct rtl9300_i2c *i2c;
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enum rtl9300_bus_freq bus_freq;
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u8 sda_pin;
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};
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#define RTL9300_I2C_MUX_NCHAN 8
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struct rtl9300_i2c {
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struct regmap *regmap;
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struct device *dev;
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struct rtl9300_i2c_chan chans[RTL9300_I2C_MUX_NCHAN];
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u32 reg_base;
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u8 sda_pin;
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struct mutex lock;
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};
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#define RTL9300_I2C_MST_CTRL1 0x0
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#define RTL9300_I2C_MST_CTRL1_MEM_ADDR_OFS 8
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#define RTL9300_I2C_MST_CTRL1_MEM_ADDR_MASK GENMASK(31, 8)
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#define RTL9300_I2C_MST_CTRL1_SDA_OUT_SEL_OFS 4
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#define RTL9300_I2C_MST_CTRL1_SDA_OUT_SEL_MASK GENMASK(6, 4)
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#define RTL9300_I2C_MST_CTRL1_GPIO_SCL_SEL BIT(3)
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#define RTL9300_I2C_MST_CTRL1_RWOP BIT(2)
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#define RTL9300_I2C_MST_CTRL1_I2C_FAIL BIT(1)
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#define RTL9300_I2C_MST_CTRL1_I2C_TRIG BIT(0)
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#define RTL9300_I2C_MST_CTRL2 0x4
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#define RTL9300_I2C_MST_CTRL2_RD_MODE BIT(15)
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#define RTL9300_I2C_MST_CTRL2_DEV_ADDR_OFS 8
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#define RTL9300_I2C_MST_CTRL2_DEV_ADDR_MASK GENMASK(14, 8)
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#define RTL9300_I2C_MST_CTRL2_DATA_WIDTH_OFS 4
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#define RTL9300_I2C_MST_CTRL2_DATA_WIDTH_MASK GENMASK(7, 4)
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#define RTL9300_I2C_MST_CTRL2_MEM_ADDR_WIDTH_OFS 2
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#define RTL9300_I2C_MST_CTRL2_MEM_ADDR_WIDTH_MASK GENMASK(3, 2)
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#define RTL9300_I2C_MST_CTRL2_SCL_FREQ_OFS 0
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#define RTL9300_I2C_MST_CTRL2_SCL_FREQ_MASK GENMASK(1, 0)
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#define RTL9300_I2C_MST_DATA_WORD0 0x8
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#define RTL9300_I2C_MST_DATA_WORD1 0xc
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#define RTL9300_I2C_MST_DATA_WORD2 0x10
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#define RTL9300_I2C_MST_DATA_WORD3 0x14
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#define RTL9300_I2C_MST_GLB_CTRL 0x384
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static int rtl9300_i2c_reg_addr_set(struct rtl9300_i2c *i2c, u32 reg, u16 len)
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{
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u32 val, mask;
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int ret;
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val = len << RTL9300_I2C_MST_CTRL2_MEM_ADDR_WIDTH_OFS;
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mask = RTL9300_I2C_MST_CTRL2_MEM_ADDR_WIDTH_MASK;
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ret = regmap_update_bits(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_CTRL2, mask, val);
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if (ret)
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return ret;
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val = reg << RTL9300_I2C_MST_CTRL1_MEM_ADDR_OFS;
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mask = RTL9300_I2C_MST_CTRL1_MEM_ADDR_MASK;
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return regmap_update_bits(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_CTRL1, mask, val);
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}
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static int rtl9300_i2c_config_io(struct rtl9300_i2c *i2c, u8 sda_pin)
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{
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int ret;
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u32 val, mask;
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ret = regmap_update_bits(i2c->regmap, RTL9300_I2C_MST_GLB_CTRL, BIT(sda_pin), BIT(sda_pin));
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if (ret)
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return ret;
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val = (sda_pin << RTL9300_I2C_MST_CTRL1_SDA_OUT_SEL_OFS) |
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RTL9300_I2C_MST_CTRL1_GPIO_SCL_SEL;
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mask = RTL9300_I2C_MST_CTRL1_SDA_OUT_SEL_MASK | RTL9300_I2C_MST_CTRL1_GPIO_SCL_SEL;
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return regmap_update_bits(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_CTRL1, mask, val);
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}
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static int rtl9300_i2c_config_xfer(struct rtl9300_i2c *i2c, struct rtl9300_i2c_chan *chan,
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u16 addr, u16 len)
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{
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u32 val, mask;
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val = chan->bus_freq << RTL9300_I2C_MST_CTRL2_SCL_FREQ_OFS;
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mask = RTL9300_I2C_MST_CTRL2_SCL_FREQ_MASK;
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val |= addr << RTL9300_I2C_MST_CTRL2_DEV_ADDR_OFS;
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mask |= RTL9300_I2C_MST_CTRL2_DEV_ADDR_MASK;
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val |= ((len - 1) & 0xf) << RTL9300_I2C_MST_CTRL2_DATA_WIDTH_OFS;
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mask |= RTL9300_I2C_MST_CTRL2_DATA_WIDTH_MASK;
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mask |= RTL9300_I2C_MST_CTRL2_RD_MODE;
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return regmap_update_bits(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_CTRL2, mask, val);
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}
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static int rtl9300_i2c_read(struct rtl9300_i2c *i2c, u8 *buf, int len)
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{
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u32 vals[4] = {};
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int i, ret;
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if (len > 16)
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return -EIO;
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ret = regmap_bulk_read(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_DATA_WORD0,
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vals, ARRAY_SIZE(vals));
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if (ret)
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return ret;
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for (i = 0; i < len; i++) {
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buf[i] = vals[i/4] & 0xff;
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vals[i/4] >>= 8;
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}
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return 0;
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}
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static int rtl9300_i2c_write(struct rtl9300_i2c *i2c, u8 *buf, int len)
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{
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u32 vals[4] = {};
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int i;
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if (len > 16)
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return -EIO;
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for (i = 0; i < len; i++) {
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if (i % 4 == 0)
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vals[i/4] = 0;
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vals[i/4] <<= 8;
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vals[i/4] |= buf[i];
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}
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return regmap_bulk_write(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_DATA_WORD0,
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vals, ARRAY_SIZE(vals));
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}
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static int rtl9300_i2c_writel(struct rtl9300_i2c *i2c, u32 data)
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{
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return regmap_write(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_DATA_WORD0, data);
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}
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static int rtl9300_i2c_execute_xfer(struct rtl9300_i2c *i2c, char read_write,
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int size, union i2c_smbus_data *data, int len)
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{
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u32 val, mask;
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int ret;
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val = read_write == I2C_SMBUS_WRITE ? RTL9300_I2C_MST_CTRL1_RWOP : 0;
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mask = RTL9300_I2C_MST_CTRL1_RWOP;
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val |= RTL9300_I2C_MST_CTRL1_I2C_TRIG;
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mask |= RTL9300_I2C_MST_CTRL1_I2C_TRIG;
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ret = regmap_update_bits(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_CTRL1, mask, val);
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if (ret)
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return ret;
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ret = regmap_read_poll_timeout(i2c->regmap, i2c->reg_base + RTL9300_I2C_MST_CTRL1,
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val, !(val & RTL9300_I2C_MST_CTRL1_I2C_TRIG), 100, 2000);
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if (ret)
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return ret;
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if (val & RTL9300_I2C_MST_CTRL1_I2C_FAIL)
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return -EIO;
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if (read_write == I2C_SMBUS_READ) {
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if (size == I2C_SMBUS_BYTE || size == I2C_SMBUS_BYTE_DATA) {
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ret = regmap_read(i2c->regmap,
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i2c->reg_base + RTL9300_I2C_MST_DATA_WORD0, &val);
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if (ret)
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return ret;
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data->byte = val & 0xff;
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} else if (size == I2C_SMBUS_WORD_DATA) {
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ret = regmap_read(i2c->regmap,
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i2c->reg_base + RTL9300_I2C_MST_DATA_WORD0, &val);
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if (ret)
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return ret;
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data->word = val & 0xffff;
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} else {
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ret = rtl9300_i2c_read(i2c, &data->block[0], len);
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if (ret)
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return ret;
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}
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}
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return 0;
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}
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static int rtl9300_i2c_smbus_xfer(struct i2c_adapter *adap, u16 addr, unsigned short flags,
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char read_write, u8 command, int size,
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union i2c_smbus_data *data)
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{
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struct rtl9300_i2c_chan *chan = i2c_get_adapdata(adap);
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struct rtl9300_i2c *i2c = chan->i2c;
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int len = 0, ret;
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mutex_lock(&i2c->lock);
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if (chan->sda_pin != i2c->sda_pin) {
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ret = rtl9300_i2c_config_io(i2c, chan->sda_pin);
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if (ret)
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goto out_unlock;
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i2c->sda_pin = chan->sda_pin;
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}
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switch (size) {
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case I2C_SMBUS_QUICK:
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ret = rtl9300_i2c_config_xfer(i2c, chan, addr, 0);
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if (ret)
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goto out_unlock;
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ret = rtl9300_i2c_reg_addr_set(i2c, 0, 0);
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if (ret)
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goto out_unlock;
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break;
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case I2C_SMBUS_BYTE:
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if (read_write == I2C_SMBUS_WRITE) {
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ret = rtl9300_i2c_config_xfer(i2c, chan, addr, 0);
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if (ret)
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goto out_unlock;
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ret = rtl9300_i2c_reg_addr_set(i2c, command, 1);
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if (ret)
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goto out_unlock;
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} else {
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ret = rtl9300_i2c_config_xfer(i2c, chan, addr, 1);
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if (ret)
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goto out_unlock;
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ret = rtl9300_i2c_reg_addr_set(i2c, 0, 0);
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if (ret)
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goto out_unlock;
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}
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break;
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case I2C_SMBUS_BYTE_DATA:
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ret = rtl9300_i2c_reg_addr_set(i2c, command, 1);
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if (ret)
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goto out_unlock;
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ret = rtl9300_i2c_config_xfer(i2c, chan, addr, 1);
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if (ret)
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goto out_unlock;
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if (read_write == I2C_SMBUS_WRITE) {
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ret = rtl9300_i2c_writel(i2c, data->byte);
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if (ret)
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goto out_unlock;
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}
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break;
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case I2C_SMBUS_WORD_DATA:
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ret = rtl9300_i2c_reg_addr_set(i2c, command, 1);
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if (ret)
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goto out_unlock;
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ret = rtl9300_i2c_config_xfer(i2c, chan, addr, 2);
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if (ret)
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goto out_unlock;
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if (read_write == I2C_SMBUS_WRITE) {
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ret = rtl9300_i2c_writel(i2c, data->word);
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if (ret)
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goto out_unlock;
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}
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break;
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case I2C_SMBUS_BLOCK_DATA:
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ret = rtl9300_i2c_reg_addr_set(i2c, command, 1);
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if (ret)
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goto out_unlock;
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ret = rtl9300_i2c_config_xfer(i2c, chan, addr, data->block[0]);
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if (ret)
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goto out_unlock;
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if (read_write == I2C_SMBUS_WRITE) {
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ret = rtl9300_i2c_write(i2c, &data->block[1], data->block[0]);
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if (ret)
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goto out_unlock;
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}
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len = data->block[0];
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break;
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default:
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dev_err(&adap->dev, "Unsupported transaction %d\n", size);
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ret = -EOPNOTSUPP;
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goto out_unlock;
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}
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ret = rtl9300_i2c_execute_xfer(i2c, read_write, size, data, len);
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out_unlock:
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mutex_unlock(&i2c->lock);
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return ret;
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}
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static u32 rtl9300_i2c_func(struct i2c_adapter *a)
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{
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return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
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I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
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I2C_FUNC_SMBUS_BLOCK_DATA;
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}
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static const struct i2c_algorithm rtl9300_i2c_algo = {
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.smbus_xfer = rtl9300_i2c_smbus_xfer,
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.functionality = rtl9300_i2c_func,
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};
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static struct i2c_adapter_quirks rtl9300_i2c_quirks = {
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.flags = I2C_AQ_NO_CLK_STRETCH,
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.max_read_len = 16,
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.max_write_len = 16,
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};
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static int rtl9300_i2c_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct rtl9300_i2c *i2c;
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u32 clock_freq, sda_pin;
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int ret, i = 0;
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struct fwnode_handle *child;
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i2c = devm_kzalloc(dev, sizeof(*i2c), GFP_KERNEL);
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if (!i2c)
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return -ENOMEM;
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i2c->regmap = syscon_node_to_regmap(dev->parent->of_node);
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if (IS_ERR(i2c->regmap))
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return PTR_ERR(i2c->regmap);
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i2c->dev = dev;
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mutex_init(&i2c->lock);
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ret = device_property_read_u32(dev, "reg", &i2c->reg_base);
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if (ret)
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return ret;
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platform_set_drvdata(pdev, i2c);
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if (device_get_child_node_count(dev) >= RTL9300_I2C_MUX_NCHAN)
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return dev_err_probe(dev, -EINVAL, "Too many channels\n");
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device_for_each_child_node(dev, child) {
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struct rtl9300_i2c_chan *chan = &i2c->chans[i];
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struct i2c_adapter *adap = &chan->adap;
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ret = fwnode_property_read_u32(child, "reg", &sda_pin);
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if (ret)
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return ret;
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ret = fwnode_property_read_u32(child, "clock-frequency", &clock_freq);
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if (ret)
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clock_freq = I2C_MAX_STANDARD_MODE_FREQ;
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switch (clock_freq) {
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case I2C_MAX_STANDARD_MODE_FREQ:
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chan->bus_freq = RTL9300_I2C_STD_FREQ;
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break;
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case I2C_MAX_FAST_MODE_FREQ:
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chan->bus_freq = RTL9300_I2C_FAST_FREQ;
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break;
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default:
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dev_warn(i2c->dev, "SDA%d clock-frequency %d not supported using default\n",
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sda_pin, clock_freq);
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break;
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}
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chan->sda_pin = sda_pin;
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chan->i2c = i2c;
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adap = &i2c->chans[i].adap;
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adap->owner = THIS_MODULE;
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adap->algo = &rtl9300_i2c_algo;
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adap->quirks = &rtl9300_i2c_quirks;
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adap->retries = 3;
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adap->dev.parent = dev;
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i2c_set_adapdata(adap, chan);
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adap->dev.of_node = to_of_node(child);
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snprintf(adap->name, sizeof(adap->name), "%s SDA%d\n", dev_name(dev), sda_pin);
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i++;
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ret = devm_i2c_add_adapter(dev, adap);
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if (ret)
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return ret;
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}
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i2c->sda_pin = 0xff;
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return 0;
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}
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static const struct of_device_id i2c_rtl9300_dt_ids[] = {
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{ .compatible = "realtek,rtl9301-i2c" },
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{ .compatible = "realtek,rtl9302b-i2c" },
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{ .compatible = "realtek,rtl9302c-i2c" },
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{ .compatible = "realtek,rtl9303-i2c" },
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{}
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};
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MODULE_DEVICE_TABLE(of, i2c_rtl9300_dt_ids);
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static struct platform_driver rtl9300_i2c_driver = {
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.probe = rtl9300_i2c_probe,
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.driver = {
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.name = "i2c-rtl9300",
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.of_match_table = i2c_rtl9300_dt_ids,
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},
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};
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module_platform_driver(rtl9300_i2c_driver);
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MODULE_DESCRIPTION("RTL9300 I2C controller driver");
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MODULE_LICENSE("GPL");
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