241 lines
8.3 KiB
C
241 lines
8.3 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Header file for UHS-II packets, Host Controller registers and I/O
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* accessors.
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*
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* Copyright (C) 2014 Intel Corp, All Rights Reserved.
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*/
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#ifndef LINUX_MMC_UHS2_H
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#define LINUX_MMC_UHS2_H
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/* LINK Layer definition */
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/*
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* UHS2 Header:
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* Refer to UHS-II Addendum Version 1.02 Figure 5-2, the format of CCMD Header is described below:
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* bit [3:0] : DID(Destination ID = Node ID of UHS2 card)
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* bit [6:4] : TYP(Packet Type)
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* 000b: CCMD(Control command packet)
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* 001b: DCMD(Data command packet)
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* 010b: RES(Response packet)
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* 011b: DATA(Data payload packet)
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* 111b: MSG(Message packet)
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* Others: Reserved
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* bit [7] : NP(Native Packet)
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* bit [10:8] : TID(Transaction ID)
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* bit [11] : Reserved
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* bit [15:12]: SID(Source ID 0: Node ID of Host)
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*
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* Broadcast CCMD issued by Host is represented as DID=SID=0.
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*/
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/*
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* UHS2 Argument:
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* Refer to UHS-II Addendum Version 1.02 Figure 6-5, the format of CCMD Argument is described below:
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* bit [3:0] : MSB of IOADR
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* bit [5:4] : PLEN(Payload Length)
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* 00b: 0 byte
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* 01b: 4 bytes
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* 10b: 8 bytes
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* 11b: 16 bytes
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* bit [6] : Reserved
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* bit [7] : R/W(Read/Write)
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* 0: Control read command
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* 1: Control write command
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* bit [15:8] : LSB of IOADR
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*
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* I/O Address specifies the address of register in UHS-II I/O space accessed by CCMD.
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* The unit of I/O Address is 4 Bytes. It is transmitted in MSB first, LSB last.
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*/
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#define UHS2_NATIVE_PACKET_POS 7
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#define UHS2_NATIVE_PACKET (1 << UHS2_NATIVE_PACKET_POS)
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#define UHS2_PACKET_TYPE_POS 4
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#define UHS2_PACKET_TYPE_CCMD (0 << UHS2_PACKET_TYPE_POS)
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#define UHS2_PACKET_TYPE_DCMD (1 << UHS2_PACKET_TYPE_POS)
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#define UHS2_PACKET_TYPE_RES (2 << UHS2_PACKET_TYPE_POS)
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#define UHS2_PACKET_TYPE_DATA (3 << UHS2_PACKET_TYPE_POS)
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#define UHS2_PACKET_TYPE_MSG (7 << UHS2_PACKET_TYPE_POS)
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#define UHS2_DEST_ID_MASK 0x0F
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#define UHS2_DEST_ID 0x1
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#define UHS2_SRC_ID_POS 12
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#define UHS2_SRC_ID_MASK 0xF000
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#define UHS2_TRANS_ID_POS 8
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#define UHS2_TRANS_ID_MASK 0x0700
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/* UHS2 MSG */
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#define UHS2_MSG_CTG_POS 5
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#define UHS2_MSG_CTG_LMSG 0x00
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#define UHS2_MSG_CTG_INT 0x60
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#define UHS2_MSG_CTG_AMSG 0x80
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#define UHS2_MSG_CTG_FCREQ 0x00
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#define UHS2_MSG_CTG_FCRDY 0x01
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#define UHS2_MSG_CTG_STAT 0x02
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#define UHS2_MSG_CODE_POS 8
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#define UHS2_MSG_CODE_FC_UNRECOVER_ERR 0x8
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#define UHS2_MSG_CODE_STAT_UNRECOVER_ERR 0x8
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#define UHS2_MSG_CODE_STAT_RECOVER_ERR 0x1
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/* TRANS Layer definition */
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/* Native packets*/
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#define UHS2_NATIVE_CMD_RW_POS 7
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#define UHS2_NATIVE_CMD_WRITE (1 << UHS2_NATIVE_CMD_RW_POS)
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#define UHS2_NATIVE_CMD_READ (0 << UHS2_NATIVE_CMD_RW_POS)
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#define UHS2_NATIVE_CMD_PLEN_POS 4
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#define UHS2_NATIVE_CMD_PLEN_4B (1 << UHS2_NATIVE_CMD_PLEN_POS)
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#define UHS2_NATIVE_CMD_PLEN_8B (2 << UHS2_NATIVE_CMD_PLEN_POS)
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#define UHS2_NATIVE_CMD_PLEN_16B (3 << UHS2_NATIVE_CMD_PLEN_POS)
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#define UHS2_NATIVE_CCMD_GET_MIOADR_MASK 0xF00
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#define UHS2_NATIVE_CCMD_MIOADR_MASK 0x0F
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#define UHS2_NATIVE_CCMD_LIOADR_POS 8
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#define UHS2_NATIVE_CCMD_GET_LIOADR_MASK 0x0FF
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#define UHS2_CCMD_DEV_INIT_COMPLETE_FLAG BIT(11)
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#define UHS2_DEV_INIT_PAYLOAD_LEN 1
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#define UHS2_DEV_INIT_RESP_LEN 6
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#define UHS2_DEV_ENUM_PAYLOAD_LEN 1
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#define UHS2_DEV_ENUM_RESP_LEN 8
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#define UHS2_CFG_WRITE_PAYLOAD_LEN 2
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#define UHS2_CFG_WRITE_PHY_SET_RESP_LEN 4
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#define UHS2_CFG_WRITE_GENERIC_SET_RESP_LEN 5
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#define UHS2_GO_DORMANT_PAYLOAD_LEN 1
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/*
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* UHS2 Argument:
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* Refer to UHS-II Addendum Version 1.02 Figure 6-8, the format of DCMD Argument is described below:
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* bit [3:0] : Reserved
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* bit [6:3] : TMODE(Transfer Mode)
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* bit 3: DAM(Data Access Mode)
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* bit 4: TLUM(TLEN Unit Mode)
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* bit 5: LM(Length Mode)
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* bit 6: DM(Duplex Mode)
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* bit [7] : R/W(Read/Write)
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* 0: Control read command
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* 1: Control write command
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* bit [15:8] : Reserved
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*
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* I/O Address specifies the address of register in UHS-II I/O space accessed by CCMD.
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* The unit of I/O Address is 4 Bytes. It is transmitted in MSB first, LSB last.
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*/
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#define UHS2_DCMD_DM_POS 6
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#define UHS2_DCMD_2L_HD_MODE (1 << UHS2_DCMD_DM_POS)
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#define UHS2_DCMD_LM_POS 5
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#define UHS2_DCMD_LM_TLEN_EXIST (1 << UHS2_DCMD_LM_POS)
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#define UHS2_DCMD_TLUM_POS 4
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#define UHS2_DCMD_TLUM_BYTE_MODE (1 << UHS2_DCMD_TLUM_POS)
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#define UHS2_NATIVE_DCMD_DAM_POS 3
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#define UHS2_NATIVE_DCMD_DAM_IO (1 << UHS2_NATIVE_DCMD_DAM_POS)
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#define UHS2_RES_NACK_POS 7
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#define UHS2_RES_NACK_MASK (0x1 << UHS2_RES_NACK_POS)
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#define UHS2_RES_ECODE_POS 4
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#define UHS2_RES_ECODE_MASK 0x7
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#define UHS2_RES_ECODE_COND 1
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#define UHS2_RES_ECODE_ARG 2
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#define UHS2_RES_ECODE_GEN 3
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/* IOADR of device registers */
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#define UHS2_IOADR_GENERIC_CAPS 0x00
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#define UHS2_IOADR_PHY_CAPS 0x02
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#define UHS2_IOADR_LINK_CAPS 0x04
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#define UHS2_IOADR_RSV_CAPS 0x06
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#define UHS2_IOADR_GENERIC_SETTINGS 0x08
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#define UHS2_IOADR_PHY_SETTINGS 0x0A
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#define UHS2_IOADR_LINK_SETTINGS 0x0C
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#define UHS2_IOADR_PRESET 0x40
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/* SD application packets */
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#define UHS2_SD_CMD_INDEX_POS 8
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#define UHS2_SD_CMD_APP_POS 14
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#define UHS2_SD_CMD_APP (1 << UHS2_SD_CMD_APP_POS)
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/* UHS-II Device Registers */
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#define UHS2_DEV_CONFIG_REG 0x000
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/* General Caps and Settings registers */
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#define UHS2_DEV_CONFIG_GEN_CAPS (UHS2_DEV_CONFIG_REG + 0x000)
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#define UHS2_DEV_CONFIG_N_LANES_POS 8
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#define UHS2_DEV_CONFIG_N_LANES_MASK 0x3F
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#define UHS2_DEV_CONFIG_2L_HD_FD 0x1
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#define UHS2_DEV_CONFIG_2D1U_FD 0x2
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#define UHS2_DEV_CONFIG_1D2U_FD 0x4
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#define UHS2_DEV_CONFIG_2D2U_FD 0x8
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#define UHS2_DEV_CONFIG_DADR_POS 14
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#define UHS2_DEV_CONFIG_DADR_MASK 0x1
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#define UHS2_DEV_CONFIG_APP_POS 16
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#define UHS2_DEV_CONFIG_APP_MASK 0xFF
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#define UHS2_DEV_CONFIG_APP_SD_MEM 0x1
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#define UHS2_DEV_CONFIG_GEN_SET (UHS2_DEV_CONFIG_REG + 0x008)
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#define UHS2_DEV_CONFIG_GEN_SET_N_LANES_POS 8
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#define UHS2_DEV_CONFIG_GEN_SET_2L_FD_HD 0x0
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#define UHS2_DEV_CONFIG_GEN_SET_2D1U_FD 0x2
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#define UHS2_DEV_CONFIG_GEN_SET_1D2U_FD 0x3
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#define UHS2_DEV_CONFIG_GEN_SET_2D2U_FD 0x4
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#define UHS2_DEV_CONFIG_GEN_SET_CFG_COMPLETE BIT(31)
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/* PHY Caps and Settings registers */
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#define UHS2_DEV_CONFIG_PHY_CAPS (UHS2_DEV_CONFIG_REG + 0x002)
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#define UHS2_DEV_CONFIG_PHY_MINOR_MASK 0xF
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#define UHS2_DEV_CONFIG_PHY_MAJOR_POS 4
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#define UHS2_DEV_CONFIG_PHY_MAJOR_MASK 0x3
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#define UHS2_DEV_CONFIG_CAN_HIBER_POS 15
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#define UHS2_DEV_CONFIG_CAN_HIBER_MASK 0x1
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#define UHS2_DEV_CONFIG_PHY_CAPS1 (UHS2_DEV_CONFIG_REG + 0x003)
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#define UHS2_DEV_CONFIG_N_LSS_SYN_MASK 0xF
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#define UHS2_DEV_CONFIG_N_LSS_DIR_POS 4
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#define UHS2_DEV_CONFIG_N_LSS_DIR_MASK 0xF
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#define UHS2_DEV_CONFIG_PHY_SET (UHS2_DEV_CONFIG_REG + 0x00A)
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#define UHS2_DEV_CONFIG_PHY_SET_SPEED_POS 6
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#define UHS2_DEV_CONFIG_PHY_SET_SPEED_A 0x0
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#define UHS2_DEV_CONFIG_PHY_SET_SPEED_B 0x1
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/* LINK-TRAN Caps and Settings registers */
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#define UHS2_DEV_CONFIG_LINK_TRAN_CAPS (UHS2_DEV_CONFIG_REG + 0x004)
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#define UHS2_DEV_CONFIG_LT_MINOR_MASK 0xF
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#define UHS2_DEV_CONFIG_LT_MAJOR_POS 4
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#define UHS2_DEV_CONFIG_LT_MAJOR_MASK 0x3
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#define UHS2_DEV_CONFIG_N_FCU_POS 8
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#define UHS2_DEV_CONFIG_N_FCU_MASK 0xFF
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#define UHS2_DEV_CONFIG_DEV_TYPE_POS 16
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#define UHS2_DEV_CONFIG_DEV_TYPE_MASK 0x7
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#define UHS2_DEV_CONFIG_MAX_BLK_LEN_POS 20
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#define UHS2_DEV_CONFIG_MAX_BLK_LEN_MASK 0xFFF
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#define UHS2_DEV_CONFIG_LINK_TRAN_CAPS1 (UHS2_DEV_CONFIG_REG + 0x005)
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#define UHS2_DEV_CONFIG_N_DATA_GAP_MASK 0xFF
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#define UHS2_DEV_CONFIG_LINK_TRAN_SET (UHS2_DEV_CONFIG_REG + 0x00C)
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#define UHS2_DEV_CONFIG_LT_SET_MAX_BLK_LEN 0x200
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#define UHS2_DEV_CONFIG_LT_SET_MAX_RETRY_POS 16
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/* Preset register */
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#define UHS2_DEV_CONFIG_PRESET (UHS2_DEV_CONFIG_REG + 0x040)
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#define UHS2_DEV_INT_REG 0x100
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#define UHS2_DEV_STATUS_REG 0x180
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#define UHS2_DEV_CMD_REG 0x200
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#define UHS2_DEV_CMD_FULL_RESET (UHS2_DEV_CMD_REG + 0x000)
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#define UHS2_DEV_CMD_GO_DORMANT_STATE (UHS2_DEV_CMD_REG + 0x001)
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#define UHS2_DEV_CMD_DORMANT_HIBER BIT(7)
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#define UHS2_DEV_CMD_DEVICE_INIT (UHS2_DEV_CMD_REG + 0x002)
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#define UHS2_DEV_INIT_COMPLETE_FLAG BIT(11)
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#define UHS2_DEV_CMD_ENUMERATE (UHS2_DEV_CMD_REG + 0x003)
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#define UHS2_DEV_CMD_TRANS_ABORT (UHS2_DEV_CMD_REG + 0x004)
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#define UHS2_RCLK_MAX 52000000
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#define UHS2_RCLK_MIN 26000000
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#endif /* LINUX_MMC_UHS2_H */
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