274 lines
6.7 KiB
C
274 lines
6.7 KiB
C
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Register Map - Based on PolarBear_CSRs.RevA.xlsx (2023-04-21)
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*
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* Copyright (C) 2023 Integrated Device Technology, Inc., a Renesas Company.
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*/
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#ifndef MFD_IDTRC38XXX_REG
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#define MFD_IDTRC38XXX_REG
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/* GLOBAL */
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#define SOFT_RESET_CTRL (0x15) /* Specific to FC3W */
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#define MISC_CTRL (0x14) /* Specific to FC3A */
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#define APLL_REINIT BIT(1)
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#define APLL_REINIT_VFC3A BIT(2)
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#define DEVICE_ID (0x2)
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#define DEVICE_ID_MASK (0x1000) /* Bit 12 is 1 if FC3W and 0 if FC3A */
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#define DEVICE_ID_SHIFT (12)
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/* FOD */
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#define FOD_0 (0x300)
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#define FOD_0_VFC3A (0x400)
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#define FOD_1 (0x340)
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#define FOD_1_VFC3A (0x440)
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#define FOD_2 (0x380)
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#define FOD_2_VFC3A (0x480)
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/* TDCAPLL */
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#define TDC_CTRL (0x44a) /* Specific to FC3W */
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#define TDC_ENABLE_CTRL (0x169) /* Specific to FC3A */
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#define TDC_DAC_CAL_CTRL (0x16a) /* Specific to FC3A */
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#define TDC_EN BIT(0)
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#define TDC_DAC_RECAL_REQ BIT(1)
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#define TDC_DAC_RECAL_REQ_VFC3A BIT(0)
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#define TDC_FB_DIV_INT_CNFG (0x442)
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#define TDC_FB_DIV_INT_CNFG_VFC3A (0x162)
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#define TDC_FB_DIV_INT_MASK GENMASK(7, 0)
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#define TDC_REF_DIV_CNFG (0x443)
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#define TDC_REF_DIV_CNFG_VFC3A (0x163)
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#define TDC_REF_DIV_CONFIG_MASK GENMASK(2, 0)
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/* TIME SYNC CHANNEL */
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#define TIME_CLOCK_SRC (0xa01) /* Specific to FC3W */
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#define TIME_CLOCK_COUNT (0xa00) /* Specific to FC3W */
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#define TIME_CLOCK_COUNT_MASK GENMASK(5, 0)
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#define SUB_SYNC_GEN_CNFG (0xa04)
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#define TOD_COUNTER_READ_REQ (0xa5f)
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#define TOD_COUNTER_READ_REQ_VFC3A (0x6df)
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#define TOD_SYNC_LOAD_VAL_CTRL (0xa10)
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#define TOD_SYNC_LOAD_VAL_CTRL_VFC3A (0x690)
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#define SYNC_COUNTER_MASK GENMASK_ULL(51, 0)
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#define SUB_SYNC_COUNTER_MASK GENMASK(30, 0)
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#define TOD_SYNC_LOAD_REQ_CTRL (0xa21)
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#define TOD_SYNC_LOAD_REQ_CTRL_VFC3A (0x6a1)
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#define SYNC_LOAD_ENABLE BIT(1)
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#define SUB_SYNC_LOAD_ENABLE BIT(0)
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#define SYNC_LOAD_REQ BIT(0)
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#define LPF_MODE_CNFG (0xa80)
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#define LPF_MODE_CNFG_VFC3A (0x700)
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enum lpf_mode {
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LPF_DISABLED = 0,
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LPF_WP = 1,
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LPF_HOLDOVER = 2,
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LPF_WF = 3,
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LPF_INVALID = 4
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};
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#define LPF_CTRL (0xa98)
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#define LPF_CTRL_VFC3A (0x718)
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#define LPF_EN BIT(0)
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#define LPF_BW_CNFG (0xa81)
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#define LPF_BW_SHIFT GENMASK(7, 3)
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#define LPF_BW_MULT GENMASK(2, 0)
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#define LPF_BW_SHIFT_DEFAULT (0xb)
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#define LPF_BW_MULT_DEFAULT (0x0)
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#define LPF_BW_SHIFT_1PPS (0x5)
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#define LPF_WR_PHASE_CTRL (0xaa8)
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#define LPF_WR_PHASE_CTRL_VFC3A (0x728)
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#define LPF_WR_FREQ_CTRL (0xab0)
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#define LPF_WR_FREQ_CTRL_VFC3A (0x730)
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#define TIME_CLOCK_TDC_FANOUT_CNFG (0xB00)
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#define TIME_SYNC_TO_TDC_EN BIT(0)
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#define SIG1_MUX_SEL_MASK GENMASK(7, 4)
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#define SIG2_MUX_SEL_MASK GENMASK(11, 8)
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enum tdc_mux_sel {
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REF0 = 0,
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REF1 = 1,
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REF2 = 2,
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REF3 = 3,
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REF_CLK5 = 4,
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REF_CLK6 = 5,
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DPLL_FB_TO_TDC = 6,
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DPLL_FB_DIVIDED_TO_TDC = 7,
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TIME_CLK_DIVIDED = 8,
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TIME_SYNC = 9,
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};
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#define TIME_CLOCK_MEAS_CNFG (0xB04)
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#define TDC_MEAS_MODE BIT(0)
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enum tdc_meas_mode {
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CONTINUOUS = 0,
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ONE_SHOT = 1,
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MEAS_MODE_INVALID = 2,
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};
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#define TIME_CLOCK_MEAS_DIV_CNFG (0xB08)
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#define TIME_REF_DIV_MASK GENMASK(29, 24)
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#define TIME_CLOCK_MEAS_CTRL (0xB10)
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#define TDC_MEAS_EN BIT(0)
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#define TDC_MEAS_START BIT(1)
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#define TDC_FIFO_READ_REQ (0xB2F)
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#define TDC_FIFO_READ (0xB30)
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#define COARSE_MEAS_MASK GENMASK_ULL(39, 13)
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#define FINE_MEAS_MASK GENMASK(12, 0)
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#define TDC_FIFO_CTRL (0xB12)
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#define FIFO_CLEAR BIT(0)
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#define TDC_FIFO_STS (0xB38)
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#define FIFO_FULL BIT(1)
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#define FIFO_EMPTY BIT(0)
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#define TDC_FIFO_EVENT (0xB39)
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#define FIFO_OVERRUN BIT(1)
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/* DPLL */
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#define MAX_REFERENCE_INDEX (3)
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#define MAX_NUM_REF_PRIORITY (4)
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#define MAX_DPLL_INDEX (2)
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#define DPLL_STS (0x580)
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#define DPLL_STS_VFC3A (0x571)
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#define DPLL_STATE_STS_MASK (0x70)
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#define DPLL_STATE_STS_SHIFT (4)
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#define DPLL_REF_SEL_STS_MASK (0x6)
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#define DPLL_REF_SEL_STS_SHIFT (1)
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#define DPLL_REF_PRIORITY_CNFG (0x502)
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#define DPLL_REFX_PRIORITY_DISABLE_MASK (0xf)
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#define DPLL_REF0_PRIORITY_ENABLE_AND_SET_MASK (0x31)
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#define DPLL_REF1_PRIORITY_ENABLE_AND_SET_MASK (0xc2)
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#define DPLL_REF2_PRIORITY_ENABLE_AND_SET_MASK (0x304)
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#define DPLL_REF3_PRIORITY_ENABLE_AND_SET_MASK (0xc08)
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#define DPLL_REF0_PRIORITY_SHIFT (4)
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#define DPLL_REF1_PRIORITY_SHIFT (6)
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#define DPLL_REF2_PRIORITY_SHIFT (8)
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#define DPLL_REF3_PRIORITY_SHIFT (10)
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enum dpll_state {
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DPLL_STATE_MIN = 0,
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DPLL_STATE_FREERUN = DPLL_STATE_MIN,
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DPLL_STATE_LOCKED = 1,
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DPLL_STATE_HOLDOVER = 2,
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DPLL_STATE_WRITE_FREQUENCY = 3,
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DPLL_STATE_ACQUIRE = 4,
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DPLL_STATE_HITLESS_SWITCH = 5,
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DPLL_STATE_MAX = DPLL_STATE_HITLESS_SWITCH
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};
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/* REFMON */
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#define LOSMON_STS_0 (0x81e)
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#define LOSMON_STS_0_VFC3A (0x18e)
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#define LOSMON_STS_1 (0x82e)
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#define LOSMON_STS_1_VFC3A (0x19e)
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#define LOSMON_STS_2 (0x83e)
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#define LOSMON_STS_2_VFC3A (0x1ae)
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#define LOSMON_STS_3 (0x84e)
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#define LOSMON_STS_3_VFC3A (0x1be)
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#define LOS_STS_MASK (0x1)
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#define FREQMON_STS_0 (0x874)
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#define FREQMON_STS_0_VFC3A (0x1d4)
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#define FREQMON_STS_1 (0x894)
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#define FREQMON_STS_1_VFC3A (0x1f4)
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#define FREQMON_STS_2 (0x8b4)
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#define FREQMON_STS_2_VFC3A (0x214)
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#define FREQMON_STS_3 (0x8d4)
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#define FREQMON_STS_3_VFC3A (0x234)
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#define FREQ_FAIL_STS_SHIFT (31)
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/* Firmware interface */
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#define TIME_CLK_FREQ_ADDR (0xffa0)
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#define XTAL_FREQ_ADDR (0xffa1)
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/*
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* Return register address and field mask based on passed in firmware version
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*/
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#define IDTFC3_FW_REG(FW, VER, REG) (((FW) < (VER)) ? (REG) : (REG##_##VER))
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#define IDTFC3_FW_FIELD(FW, VER, FIELD) (((FW) < (VER)) ? (FIELD) : (FIELD##_##VER))
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enum fw_version {
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V_DEFAULT = 0,
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VFC3W = 1,
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VFC3A = 2
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};
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/* XTAL_FREQ_ADDR/TIME_CLK_FREQ_ADDR */
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enum {
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FREQ_MIN = 0,
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FREQ_25M = 1,
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FREQ_49_152M = 2,
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FREQ_50M = 3,
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FREQ_100M = 4,
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FREQ_125M = 5,
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FREQ_250M = 6,
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FREQ_MAX
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};
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struct idtfc3_hw_param {
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u32 xtal_freq;
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u32 time_clk_freq;
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};
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struct idtfc3_fwrc {
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u8 hiaddr;
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u8 loaddr;
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u8 value;
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u8 reserved;
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} __packed;
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static inline void idtfc3_default_hw_param(struct idtfc3_hw_param *hw_param)
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{
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hw_param->xtal_freq = 49152000;
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hw_param->time_clk_freq = 25000000;
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}
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static inline int idtfc3_set_hw_param(struct idtfc3_hw_param *hw_param,
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u16 addr, u8 val)
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{
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if (addr == XTAL_FREQ_ADDR)
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switch (val) {
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case FREQ_49_152M:
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hw_param->xtal_freq = 49152000;
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break;
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case FREQ_50M:
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hw_param->xtal_freq = 50000000;
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break;
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default:
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return -EINVAL;
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}
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else if (addr == TIME_CLK_FREQ_ADDR)
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switch (val) {
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case FREQ_25M:
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hw_param->time_clk_freq = 25000000;
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break;
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case FREQ_50M:
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hw_param->time_clk_freq = 50000000;
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break;
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case FREQ_100M:
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hw_param->time_clk_freq = 100000000;
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break;
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case FREQ_125M:
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hw_param->time_clk_freq = 125000000;
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break;
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case FREQ_250M:
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hw_param->time_clk_freq = 250000000;
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break;
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default:
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return -EINVAL;
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}
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else
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return -EFAULT;
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return 0;
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}
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#endif
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