53 lines
1.8 KiB
C
53 lines
1.8 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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#ifndef __LINUX_IRQCHIP_ARM_GIC_V3_PRIO_H
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#define __LINUX_IRQCHIP_ARM_GIC_V3_PRIO_H
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/*
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* GIC priorities from the view of the PMR/RPR.
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*
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* These values are chosen to be valid in either the absolute priority space or
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* the NS view of the priority space. The value programmed into the distributor
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* and ITS will be chosen at boot time such that these values appear in the
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* PMR/RPR.
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*
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* GICV3_PRIO_UNMASKED is the PMR view of the priority to use to permit both
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* IRQs and pseudo-NMIs.
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*
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* GICV3_PRIO_IRQ is the PMR view of the priority of regular interrupts. This
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* can be written to the PMR to mask regular IRQs.
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*
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* GICV3_PRIO_NMI is the PMR view of the priority of pseudo-NMIs. This can be
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* written to the PMR to mask pseudo-NMIs.
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*
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* On arm64 some code sections either automatically switch back to PSR.I or
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* explicitly require to not use priority masking. If bit GICV3_PRIO_PSR_I_SET
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* is included in the priority mask, it indicates that PSR.I should be set and
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* interrupt disabling temporarily does not rely on IRQ priorities.
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*/
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#define GICV3_PRIO_UNMASKED 0xe0
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#define GICV3_PRIO_IRQ 0xc0
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#define GICV3_PRIO_NMI 0x80
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#define GICV3_PRIO_PSR_I_SET (1 << 4)
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#ifndef __ASSEMBLER__
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#define __gicv3_prio_to_ns(p) (0xff & ((p) << 1))
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#define __gicv3_ns_to_prio(ns) (0x80 | ((ns) >> 1))
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#define __gicv3_prio_valid_ns(p) \
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(__gicv3_ns_to_prio(__gicv3_prio_to_ns(p)) == (p))
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static_assert(__gicv3_prio_valid_ns(GICV3_PRIO_NMI));
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static_assert(__gicv3_prio_valid_ns(GICV3_PRIO_IRQ));
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static_assert(GICV3_PRIO_NMI < GICV3_PRIO_IRQ);
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static_assert(GICV3_PRIO_IRQ < GICV3_PRIO_UNMASKED);
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static_assert(GICV3_PRIO_IRQ < (GICV3_PRIO_IRQ | GICV3_PRIO_PSR_I_SET));
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#endif /* __ASSEMBLER */
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#endif /* __LINUX_IRQCHIP_ARM_GIC_V3_PRIO_H */
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