81 lines
2.2 KiB
C
81 lines
2.2 KiB
C
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* rzg2l-cru-regs.h--RZ/G2L (and alike SoCs) CRU Registers Definitions
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*
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* Copyright (C) 2024 Renesas Electronics Corp.
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*/
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#ifndef __RZG2L_CRU_REGS_H__
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#define __RZG2L_CRU_REGS_H__
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/* HW CRU Registers Definition */
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/* CRU Control Register */
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#define CRUnCTRL 0x0
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#define CRUnCTRL_VINSEL(x) ((x) << 0)
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/* CRU Interrupt Enable Register */
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#define CRUnIE 0x4
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#define CRUnIE_EFE BIT(17)
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/* CRU Interrupt Status Register */
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#define CRUnINTS 0x8
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#define CRUnINTS_SFS BIT(16)
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/* CRU Reset Register */
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#define CRUnRST 0xc
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#define CRUnRST_VRESETN BIT(0)
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/* Memory Bank Base Address (Lower) Register for CRU Image Data */
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#define AMnMBxADDRL(x) (0x100 + ((x) * 8))
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/* Memory Bank Base Address (Higher) Register for CRU Image Data */
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#define AMnMBxADDRH(x) (0x104 + ((x) * 8))
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/* Memory Bank Enable Register for CRU Image Data */
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#define AMnMBVALID 0x148
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#define AMnMBVALID_MBVALID(x) GENMASK(x, 0)
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/* Memory Bank Status Register for CRU Image Data */
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#define AMnMBS 0x14c
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#define AMnMBS_MBSTS 0x7
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/* AXI Master Transfer Setting Register for CRU Image Data */
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#define AMnAXIATTR 0x158
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#define AMnAXIATTR_AXILEN_MASK GENMASK(3, 0)
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#define AMnAXIATTR_AXILEN (0xf)
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/* AXI Master FIFO Pointer Register for CRU Image Data */
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#define AMnFIFOPNTR 0x168
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#define AMnFIFOPNTR_FIFOWPNTR GENMASK(7, 0)
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#define AMnFIFOPNTR_FIFORPNTR_Y GENMASK(23, 16)
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/* AXI Master Transfer Stop Register for CRU Image Data */
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#define AMnAXISTP 0x174
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#define AMnAXISTP_AXI_STOP BIT(0)
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/* AXI Master Transfer Stop Status Register for CRU Image Data */
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#define AMnAXISTPACK 0x178
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#define AMnAXISTPACK_AXI_STOP_ACK BIT(0)
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/* CRU Image Processing Enable Register */
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#define ICnEN 0x200
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#define ICnEN_ICEN BIT(0)
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/* CRU Image Processing Main Control Register */
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#define ICnMC 0x208
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#define ICnMC_CSCTHR BIT(5)
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#define ICnMC_INF(x) ((x) << 16)
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#define ICnMC_VCSEL(x) ((x) << 22)
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#define ICnMC_INF_MASK GENMASK(21, 16)
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/* CRU Module Status Register */
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#define ICnMS 0x254
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#define ICnMS_IA BIT(2)
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/* CRU Data Output Mode Register */
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#define ICnDMR 0x26c
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#define ICnDMR_YCMODE_UYVY (1 << 4)
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#endif /* __RZG2L_CRU_REGS_H__ */
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