454 lines
18 KiB
C
454 lines
18 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (C) 2024 Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
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* Author: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
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*
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* Device Tree binding constants for Exynos8895 clock controller.
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*/
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#ifndef _DT_BINDINGS_CLOCK_EXYNOS8895_H
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#define _DT_BINDINGS_CLOCK_EXYNOS8895_H
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/* CMU_TOP */
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#define CLK_FOUT_SHARED0_PLL 1
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#define CLK_FOUT_SHARED1_PLL 2
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#define CLK_FOUT_SHARED2_PLL 3
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#define CLK_FOUT_SHARED3_PLL 4
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#define CLK_FOUT_SHARED4_PLL 5
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#define CLK_MOUT_PLL_SHARED0 6
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#define CLK_MOUT_PLL_SHARED1 7
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#define CLK_MOUT_PLL_SHARED2 8
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#define CLK_MOUT_PLL_SHARED3 9
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#define CLK_MOUT_PLL_SHARED4 10
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#define CLK_MOUT_CP2AP_MIF_CLK_USER 11
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#define CLK_MOUT_CMU_ABOX_CPUABOX 12
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#define CLK_MOUT_CMU_APM_BUS 13
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#define CLK_MOUT_CMU_BUS1_BUS 14
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#define CLK_MOUT_CMU_BUSC_BUS 15
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#define CLK_MOUT_CMU_BUSC_BUSPHSI2C 16
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#define CLK_MOUT_CMU_CAM_BUS 17
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#define CLK_MOUT_CMU_CAM_TPU0 18
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#define CLK_MOUT_CMU_CAM_TPU1 19
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#define CLK_MOUT_CMU_CAM_VRA 20
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#define CLK_MOUT_CMU_CIS_CLK0 21
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#define CLK_MOUT_CMU_CIS_CLK1 22
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#define CLK_MOUT_CMU_CIS_CLK2 23
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#define CLK_MOUT_CMU_CIS_CLK3 24
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#define CLK_MOUT_CMU_CORE_BUS 25
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#define CLK_MOUT_CMU_CPUCL0_SWITCH 26
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#define CLK_MOUT_CMU_CPUCL1_SWITCH 27
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#define CLK_MOUT_CMU_DBG_BUS 28
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#define CLK_MOUT_CMU_DCAM_BUS 29
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#define CLK_MOUT_CMU_DCAM_IMGD 30
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#define CLK_MOUT_CMU_DPU_BUS 31
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#define CLK_MOUT_CMU_DROOPDETECTOR 32
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#define CLK_MOUT_CMU_DSP_BUS 33
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#define CLK_MOUT_CMU_FSYS0_BUS 34
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#define CLK_MOUT_CMU_FSYS0_DPGTC 35
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#define CLK_MOUT_CMU_FSYS0_MMC_EMBD 36
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#define CLK_MOUT_CMU_FSYS0_UFS_EMBD 37
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#define CLK_MOUT_CMU_FSYS0_USBDRD30 38
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#define CLK_MOUT_CMU_FSYS1_BUS 39
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#define CLK_MOUT_CMU_FSYS1_MMC_CARD 40
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#define CLK_MOUT_CMU_FSYS1_PCIE 41
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#define CLK_MOUT_CMU_FSYS1_UFS_CARD 42
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#define CLK_MOUT_CMU_G2D_G2D 43
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#define CLK_MOUT_CMU_G2D_JPEG 44
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#define CLK_MOUT_CMU_HPM 45
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#define CLK_MOUT_CMU_IMEM_BUS 46
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#define CLK_MOUT_CMU_ISPHQ_BUS 47
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#define CLK_MOUT_CMU_ISPLP_BUS 48
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#define CLK_MOUT_CMU_IVA_BUS 49
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#define CLK_MOUT_CMU_MFC_BUS 50
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#define CLK_MOUT_CMU_MIF_SWITCH 51
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#define CLK_MOUT_CMU_PERIC0_BUS 52
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#define CLK_MOUT_CMU_PERIC0_UART_DBG 53
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#define CLK_MOUT_CMU_PERIC0_USI00 54
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#define CLK_MOUT_CMU_PERIC0_USI01 55
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#define CLK_MOUT_CMU_PERIC0_USI02 56
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#define CLK_MOUT_CMU_PERIC0_USI03 57
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#define CLK_MOUT_CMU_PERIC1_BUS 58
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#define CLK_MOUT_CMU_PERIC1_SPEEDY2 59
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#define CLK_MOUT_CMU_PERIC1_SPI_CAM0 60
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#define CLK_MOUT_CMU_PERIC1_SPI_CAM1 61
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#define CLK_MOUT_CMU_PERIC1_UART_BT 62
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#define CLK_MOUT_CMU_PERIC1_USI04 63
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#define CLK_MOUT_CMU_PERIC1_USI05 64
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#define CLK_MOUT_CMU_PERIC1_USI06 65
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#define CLK_MOUT_CMU_PERIC1_USI07 66
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#define CLK_MOUT_CMU_PERIC1_USI08 67
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#define CLK_MOUT_CMU_PERIC1_USI09 68
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#define CLK_MOUT_CMU_PERIC1_USI10 69
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#define CLK_MOUT_CMU_PERIC1_USI11 70
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#define CLK_MOUT_CMU_PERIC1_USI12 71
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#define CLK_MOUT_CMU_PERIC1_USI13 72
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#define CLK_MOUT_CMU_PERIS_BUS 73
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#define CLK_MOUT_CMU_SRDZ_BUS 74
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#define CLK_MOUT_CMU_SRDZ_IMGD 75
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#define CLK_MOUT_CMU_VPU_BUS 76
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#define CLK_DOUT_CMU_ABOX_CPUABOX 77
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#define CLK_DOUT_CMU_APM_BUS 78
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#define CLK_DOUT_CMU_BUS1_BUS 79
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#define CLK_DOUT_CMU_BUSC_BUS 80
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#define CLK_DOUT_CMU_BUSC_BUSPHSI2C 81
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#define CLK_DOUT_CMU_CAM_BUS 82
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#define CLK_DOUT_CMU_CAM_TPU0 83
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#define CLK_DOUT_CMU_CAM_TPU1 84
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#define CLK_DOUT_CMU_CAM_VRA 85
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#define CLK_DOUT_CMU_CIS_CLK0 86
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#define CLK_DOUT_CMU_CIS_CLK1 87
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#define CLK_DOUT_CMU_CIS_CLK2 88
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#define CLK_DOUT_CMU_CIS_CLK3 89
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#define CLK_DOUT_CMU_CORE_BUS 90
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#define CLK_DOUT_CMU_CPUCL0_SWITCH 91
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#define CLK_DOUT_CMU_CPUCL1_SWITCH 92
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#define CLK_DOUT_CMU_DBG_BUS 93
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#define CLK_DOUT_CMU_DCAM_BUS 94
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#define CLK_DOUT_CMU_DCAM_IMGD 95
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#define CLK_DOUT_CMU_DPU_BUS 96
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#define CLK_DOUT_CMU_DSP_BUS 97
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#define CLK_DOUT_CMU_FSYS0_BUS 98
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#define CLK_DOUT_CMU_FSYS0_DPGTC 99
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#define CLK_DOUT_CMU_FSYS0_MMC_EMBD 100
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#define CLK_DOUT_CMU_FSYS0_UFS_EMBD 101
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#define CLK_DOUT_CMU_FSYS0_USBDRD30 102
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#define CLK_DOUT_CMU_FSYS1_BUS 103
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#define CLK_DOUT_CMU_FSYS1_MMC_CARD 104
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#define CLK_DOUT_CMU_FSYS1_UFS_CARD 105
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#define CLK_DOUT_CMU_G2D_G2D 106
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#define CLK_DOUT_CMU_G2D_JPEG 107
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#define CLK_DOUT_CMU_G3D_SWITCH 108
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#define CLK_DOUT_CMU_HPM 109
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#define CLK_DOUT_CMU_IMEM_BUS 110
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#define CLK_DOUT_CMU_ISPHQ_BUS 111
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#define CLK_DOUT_CMU_ISPLP_BUS 112
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#define CLK_DOUT_CMU_IVA_BUS 113
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#define CLK_DOUT_CMU_MFC_BUS 114
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#define CLK_DOUT_CMU_MODEM_SHARED0 115
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#define CLK_DOUT_CMU_MODEM_SHARED1 116
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#define CLK_DOUT_CMU_PERIC0_BUS 117
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#define CLK_DOUT_CMU_PERIC0_UART_DBG 118
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#define CLK_DOUT_CMU_PERIC0_USI00 119
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#define CLK_DOUT_CMU_PERIC0_USI01 120
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#define CLK_DOUT_CMU_PERIC0_USI02 121
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#define CLK_DOUT_CMU_PERIC0_USI03 122
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#define CLK_DOUT_CMU_PERIC1_BUS 123
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#define CLK_DOUT_CMU_PERIC1_SPEEDY2 124
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#define CLK_DOUT_CMU_PERIC1_SPI_CAM0 125
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#define CLK_DOUT_CMU_PERIC1_SPI_CAM1 126
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#define CLK_DOUT_CMU_PERIC1_UART_BT 127
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#define CLK_DOUT_CMU_PERIC1_USI04 128
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#define CLK_DOUT_CMU_PERIC1_USI05 129
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#define CLK_DOUT_CMU_PERIC1_USI06 130
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#define CLK_DOUT_CMU_PERIC1_USI07 131
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#define CLK_DOUT_CMU_PERIC1_USI08 132
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#define CLK_DOUT_CMU_PERIC1_USI09 133
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#define CLK_DOUT_CMU_PERIC1_USI10 134
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#define CLK_DOUT_CMU_PERIC1_USI11 135
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#define CLK_DOUT_CMU_PERIC1_USI12 136
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#define CLK_DOUT_CMU_PERIC1_USI13 137
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#define CLK_DOUT_CMU_PERIS_BUS 138
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#define CLK_DOUT_CMU_SRDZ_BUS 139
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#define CLK_DOUT_CMU_SRDZ_IMGD 140
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#define CLK_DOUT_CMU_VPU_BUS 141
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#define CLK_DOUT_CMU_SHARED0_DIV2 142
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#define CLK_DOUT_CMU_SHARED0_DIV4 143
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#define CLK_DOUT_CMU_SHARED1_DIV2 144
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#define CLK_DOUT_CMU_SHARED1_DIV4 145
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#define CLK_DOUT_CMU_SHARED2_DIV2 146
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#define CLK_DOUT_CMU_SHARED3_DIV2 147
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#define CLK_DOUT_CMU_SHARED4_DIV2 148
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#define CLK_DOUT_CMU_FSYS1_PCIE 149
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#define CLK_DOUT_CMU_CP2AP_MIF_CLK_DIV2 150
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#define CLK_DOUT_CMU_CMU_OTP 151
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#define CLK_GOUT_CMU_DROOPDETECTOR 152
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#define CLK_GOUT_CMU_MIF_SWITCH 153
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#define CLK_GOUT_CMU_ABOX_CPUABOX 154
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#define CLK_GOUT_CMU_APM_BUS 155
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#define CLK_GOUT_CMU_BUS1_BUS 156
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#define CLK_GOUT_CMU_BUSC_BUS 157
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#define CLK_GOUT_CMU_BUSC_BUSPHSI2C 158
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#define CLK_GOUT_CMU_CAM_BUS 159
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#define CLK_GOUT_CMU_CAM_TPU0 160
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#define CLK_GOUT_CMU_CAM_TPU1 161
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#define CLK_GOUT_CMU_CAM_VRA 162
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#define CLK_GOUT_CMU_CIS_CLK0 163
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#define CLK_GOUT_CMU_CIS_CLK1 164
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#define CLK_GOUT_CMU_CIS_CLK2 165
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#define CLK_GOUT_CMU_CIS_CLK3 166
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#define CLK_GOUT_CMU_CORE_BUS 167
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#define CLK_GOUT_CMU_CPUCL0_SWITCH 168
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#define CLK_GOUT_CMU_CPUCL1_SWITCH 169
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#define CLK_GOUT_CMU_DBG_BUS 170
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#define CLK_GOUT_CMU_DCAM_BUS 171
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#define CLK_GOUT_CMU_DCAM_IMGD 172
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#define CLK_GOUT_CMU_DPU_BUS 173
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#define CLK_GOUT_CMU_DSP_BUS 174
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#define CLK_GOUT_CMU_FSYS0_BUS 175
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#define CLK_GOUT_CMU_FSYS0_DPGTC 176
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#define CLK_GOUT_CMU_FSYS0_MMC_EMBD 177
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#define CLK_GOUT_CMU_FSYS0_UFS_EMBD 178
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#define CLK_GOUT_CMU_FSYS0_USBDRD30 179
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#define CLK_GOUT_CMU_FSYS1_BUS 180
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#define CLK_GOUT_CMU_FSYS1_MMC_CARD 181
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#define CLK_GOUT_CMU_FSYS1_PCIE 182
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#define CLK_GOUT_CMU_FSYS1_UFS_CARD 183
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#define CLK_GOUT_CMU_G2D_G2D 184
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#define CLK_GOUT_CMU_G2D_JPEG 185
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#define CLK_GOUT_CMU_G3D_SWITCH 186
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#define CLK_GOUT_CMU_HPM 187
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#define CLK_GOUT_CMU_IMEM_BUS 188
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#define CLK_GOUT_CMU_ISPHQ_BUS 189
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#define CLK_GOUT_CMU_ISPLP_BUS 190
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#define CLK_GOUT_CMU_IVA_BUS 191
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#define CLK_GOUT_CMU_MFC_BUS 192
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#define CLK_GOUT_CMU_MODEM_SHARED0 193
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#define CLK_GOUT_CMU_MODEM_SHARED1 194
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#define CLK_GOUT_CMU_PERIC0_BUS 195
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#define CLK_GOUT_CMU_PERIC0_UART_DBG 196
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#define CLK_GOUT_CMU_PERIC0_USI00 197
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#define CLK_GOUT_CMU_PERIC0_USI01 198
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#define CLK_GOUT_CMU_PERIC0_USI02 199
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#define CLK_GOUT_CMU_PERIC0_USI03 200
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#define CLK_GOUT_CMU_PERIC1_BUS 201
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#define CLK_GOUT_CMU_PERIC1_SPEEDY2 202
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#define CLK_GOUT_CMU_PERIC1_SPI_CAM0 203
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#define CLK_GOUT_CMU_PERIC1_SPI_CAM1 204
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#define CLK_GOUT_CMU_PERIC1_UART_BT 205
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#define CLK_GOUT_CMU_PERIC1_USI04 206
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#define CLK_GOUT_CMU_PERIC1_USI05 207
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#define CLK_GOUT_CMU_PERIC1_USI06 208
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#define CLK_GOUT_CMU_PERIC1_USI07 209
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#define CLK_GOUT_CMU_PERIC1_USI08 210
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#define CLK_GOUT_CMU_PERIC1_USI09 211
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#define CLK_GOUT_CMU_PERIC1_USI10 212
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#define CLK_GOUT_CMU_PERIC1_USI11 213
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#define CLK_GOUT_CMU_PERIC1_USI12 214
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#define CLK_GOUT_CMU_PERIC1_USI13 215
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#define CLK_GOUT_CMU_PERIS_BUS 216
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#define CLK_GOUT_CMU_SRDZ_BUS 217
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#define CLK_GOUT_CMU_SRDZ_IMGD 218
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#define CLK_GOUT_CMU_VPU_BUS 219
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/* CMU_PERIS */
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#define CLK_MOUT_PERIS_BUS_USER 1
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#define CLK_MOUT_PERIS_GIC 2
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#define CLK_GOUT_PERIS_CMU_PERIS_PCLK 3
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#define CLK_GOUT_PERIS_AD_AXI_P_PERIS_ACLKM 4
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#define CLK_GOUT_PERIS_AD_AXI_P_PERIS_ACLKS 5
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#define CLK_GOUT_PERIS_AXI2APB_PERISP0_ACLK 6
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#define CLK_GOUT_PERIS_AXI2APB_PERISP1_ACLK 7
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#define CLK_GOUT_PERIS_BUSIF_TMU_PCLK 8
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#define CLK_GOUT_PERIS_GIC_CLK 9
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#define CLK_GOUT_PERIS_LHM_AXI_P_PERIS_I_CLK 10
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#define CLK_GOUT_PERIS_MCT_PCLK 11
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#define CLK_GOUT_PERIS_OTP_CON_BIRA_PCLK 12
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#define CLK_GOUT_PERIS_OTP_CON_TOP_PCLK 13
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#define CLK_GOUT_PERIS_PMU_PERIS_PCLK 14
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#define CLK_GOUT_PERIS_RSTNSYNC_CLK_PERIS_BUSP_CLK 15
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#define CLK_GOUT_PERIS_RSTNSYNC_CLK_PERIS_GIC_CLK 16
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#define CLK_GOUT_PERIS_SYSREG_PERIS_PCLK 17
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#define CLK_GOUT_PERIS_TZPC00_PCLK 18
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#define CLK_GOUT_PERIS_TZPC01_PCLK 19
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#define CLK_GOUT_PERIS_TZPC02_PCLK 20
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#define CLK_GOUT_PERIS_TZPC03_PCLK 21
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#define CLK_GOUT_PERIS_TZPC04_PCLK 22
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#define CLK_GOUT_PERIS_TZPC05_PCLK 23
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#define CLK_GOUT_PERIS_TZPC06_PCLK 24
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#define CLK_GOUT_PERIS_TZPC07_PCLK 25
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#define CLK_GOUT_PERIS_TZPC08_PCLK 26
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#define CLK_GOUT_PERIS_TZPC09_PCLK 27
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#define CLK_GOUT_PERIS_TZPC10_PCLK 28
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#define CLK_GOUT_PERIS_TZPC11_PCLK 29
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#define CLK_GOUT_PERIS_TZPC12_PCLK 30
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#define CLK_GOUT_PERIS_TZPC13_PCLK 31
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#define CLK_GOUT_PERIS_TZPC14_PCLK 32
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#define CLK_GOUT_PERIS_TZPC15_PCLK 33
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#define CLK_GOUT_PERIS_WDT_CLUSTER0_PCLK 34
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#define CLK_GOUT_PERIS_WDT_CLUSTER1_PCLK 35
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#define CLK_GOUT_PERIS_XIU_P_PERIS_ACLK 36
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/* CMU_FSYS0 */
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#define CLK_MOUT_FSYS0_BUS_USER 1
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#define CLK_MOUT_FSYS0_DPGTC_USER 2
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#define CLK_MOUT_FSYS0_MMC_EMBD_USER 3
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#define CLK_MOUT_FSYS0_UFS_EMBD_USER 4
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#define CLK_MOUT_FSYS0_USBDRD30_USER 5
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#define CLK_GOUT_FSYS0_FSYS0_CMU_FSYS0_PCLK 6
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#define CLK_GOUT_FSYS0_AHBBR_FSYS0_HCLK 7
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#define CLK_GOUT_FSYS0_AXI2AHB_FSYS0_ACLK 8
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#define CLK_GOUT_FSYS0_AXI2AHB_USB_FSYS0_ACLK 9
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#define CLK_GOUT_FSYS0_AXI2APB_FSYS0_ACLK 10
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#define CLK_GOUT_FSYS0_BTM_FSYS0_I_ACLK 11
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#define CLK_GOUT_FSYS0_BTM_FSYS0_I_PCLK 12
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#define CLK_GOUT_FSYS0_DP_LINK_I_GTC_EXT_CLK 13
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#define CLK_GOUT_FSYS0_DP_LINK_I_PCLK 14
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#define CLK_GOUT_FSYS0_ETR_MIU_I_ACLK 15
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#define CLK_GOUT_FSYS0_ETR_MIU_I_PCLK 16
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#define CLK_GOUT_FSYS0_GPIO_FSYS0_PCLK 17
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#define CLK_GOUT_FSYS0_LHM_AXI_D_USBTV_I_CLK 18
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#define CLK_GOUT_FSYS0_LHM_AXI_G_ETR_I_CLK 19
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#define CLK_GOUT_FSYS0_LHM_AXI_P_FSYS0_I_CLK 20
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#define CLK_GOUT_FSYS0_LHS_ACEL_D_FSYS0_I_CLK 21
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#define CLK_GOUT_FSYS0_MMC_EMBD_I_ACLK 22
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#define CLK_GOUT_FSYS0_MMC_EMBD_SDCLKIN 23
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#define CLK_GOUT_FSYS0_PMU_FSYS0_PCLK 24
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#define CLK_GOUT_FSYS0_BCM_FSYS0_ACLK 25
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#define CLK_GOUT_FSYS0_BCM_FSYS0_PCLK 26
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#define CLK_GOUT_FSYS0_RSTNSYNC_CLK_FSYS0_BUS_CLK 27
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#define CLK_GOUT_FSYS0_SYSREG_FSYS0_PCLK 28
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#define CLK_GOUT_FSYS0_UFS_EMBD_I_ACLK 29
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#define CLK_GOUT_FSYS0_UFS_EMBD_I_CLK_UNIPRO 30
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#define CLK_GOUT_FSYS0_UFS_EMBD_I_FMP_CLK 31
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#define CLK_GOUT_FSYS0_USBTV_I_USB30DRD_ACLK 32
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#define CLK_GOUT_FSYS0_USBTV_I_USB30DRD_REF_CLK 33
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#define CLK_GOUT_FSYS0_USBTV_I_USB30DRD_SUSPEND_CLK 34
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#define CLK_GOUT_FSYS0_USBTV_I_USBTVH_AHB_CLK 35
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#define CLK_GOUT_FSYS0_USBTV_I_USBTVH_CORE_CLK 36
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#define CLK_GOUT_FSYS0_USBTV_I_USBTVH_XIU_CLK 37
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#define CLK_GOUT_FSYS0_US_D_FSYS0_USB_ACLK 38
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#define CLK_GOUT_FSYS0_XIU_D_FSYS0_ACLK 39
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#define CLK_GOUT_FSYS0_XIU_D_FSYS0_USB_ACLK 40
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#define CLK_GOUT_FSYS0_XIU_P_FSYS0_ACLK 41
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/* CMU_FSYS1 */
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#define CLK_MOUT_FSYS1_BUS_USER 1
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#define CLK_MOUT_FSYS1_MMC_CARD_USER 2
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#define CLK_MOUT_FSYS1_PCIE_USER 3
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#define CLK_MOUT_FSYS1_UFS_CARD_USER 4
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#define CLK_GOUT_FSYS1_PCIE_PHY_REF_CLK_IN 5
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#define CLK_GOUT_FSYS1_ADM_AHB_SSS_HCLKM 6
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#define CLK_GOUT_FSYS1_AHBBR_FSYS1_HCLK 7
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#define CLK_GOUT_FSYS1_AXI2AHB_FSYS1_ACLK 8
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#define CLK_GOUT_FSYS1_AXI2APB_FSYS1P0_ACLK 9
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#define CLK_GOUT_FSYS1_AXI2APB_FSYS1P1_ACLK 10
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#define CLK_GOUT_FSYS1_BTM_FSYS1_I_ACLK 11
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#define CLK_GOUT_FSYS1_BTM_FSYS1_I_PCLK 12
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#define CLK_GOUT_FSYS1_FSYS1_CMU_FSYS1_PCLK 13
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#define CLK_GOUT_FSYS1_GPIO_FSYS1_PCLK 14
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#define CLK_GOUT_FSYS1_LHM_AXI_P_FSYS1_I_CLK 15
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#define CLK_GOUT_FSYS1_LHS_ACEL_D_FSYS1_I_CLK 16
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#define CLK_GOUT_FSYS1_MMC_CARD_I_ACLK 17
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#define CLK_GOUT_FSYS1_MMC_CARD_SDCLKIN 18
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#define CLK_GOUT_FSYS1_PCIE_DBI_ACLK_0 19
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#define CLK_GOUT_FSYS1_PCIE_DBI_ACLK_1 20
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#define CLK_GOUT_FSYS1_PCIE_IEEE1500_WRAPPER_FOR_PCIE_PHY_LC_X2_INST_0_I_SCL_APB_PCLK 21
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#define CLK_GOUT_FSYS1_PCIE_MSTR_ACLK_0 22
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#define CLK_GOUT_FSYS1_PCIE_MSTR_ACLK_1 23
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#define CLK_GOUT_FSYS1_PCIE_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK 24
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#define CLK_GOUT_FSYS1_PCIE_PCIE_SUB_CTRL_INST_1_I_DRIVER_APB_CLK 25
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#define CLK_GOUT_FSYS1_PCIE_PIPE2_DIGITAL_X2_WRAP_INST_0_I_APB_PCLK_SCL 26
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#define CLK_GOUT_FSYS1_PCIE_SLV_ACLK_0 27
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#define CLK_GOUT_FSYS1_PCIE_SLV_ACLK_1 28
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#define CLK_GOUT_FSYS1_PMU_FSYS1_PCLK 29
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#define CLK_GOUT_FSYS1_BCM_FSYS1_ACLK 30
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#define CLK_GOUT_FSYS1_BCM_FSYS1_PCLK 31
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#define CLK_GOUT_FSYS1_RSTNSYNC_CLK_FSYS1_BUS_CLK 32
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#define CLK_GOUT_FSYS1_RTIC_I_ACLK 33
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#define CLK_GOUT_FSYS1_RTIC_I_PCLK 34
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#define CLK_GOUT_FSYS1_SSS_I_ACLK 35
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#define CLK_GOUT_FSYS1_SSS_I_PCLK 36
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#define CLK_GOUT_FSYS1_SYSREG_FSYS1_PCLK 37
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#define CLK_GOUT_FSYS1_TOE_WIFI0_I_CLK 38
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#define CLK_GOUT_FSYS1_TOE_WIFI1_I_CLK 39
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#define CLK_GOUT_FSYS1_UFS_CARD_I_ACLK 40
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#define CLK_GOUT_FSYS1_UFS_CARD_I_CLK_UNIPRO 41
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#define CLK_GOUT_FSYS1_UFS_CARD_I_FMP_CLK 42
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#define CLK_GOUT_FSYS1_XIU_D_FSYS1_ACLK 43
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#define CLK_GOUT_FSYS1_XIU_P_FSYS1_ACLK 44
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/* CMU_PERIC0 */
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#define CLK_MOUT_PERIC0_BUS_USER 1
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#define CLK_MOUT_PERIC0_UART_DBG_USER 2
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#define CLK_MOUT_PERIC0_USI00_USER 3
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#define CLK_MOUT_PERIC0_USI01_USER 4
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#define CLK_MOUT_PERIC0_USI02_USER 5
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#define CLK_MOUT_PERIC0_USI03_USER 6
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#define CLK_GOUT_PERIC0_PERIC0_CMU_PERIC0_PCLK 7
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#define CLK_GOUT_PERIC0_AXI2APB_PERIC0_ACLK 8
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#define CLK_GOUT_PERIC0_GPIO_PERIC0_PCLK 9
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#define CLK_GOUT_PERIC0_LHM_AXI_P_PERIC0_I_CLK 10
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#define CLK_GOUT_PERIC0_PMU_PERIC0_PCLK 11
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#define CLK_GOUT_PERIC0_PWM_I_PCLK_S0 12
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#define CLK_GOUT_PERIC0_RSTNSYNC_CLK_PERIC0_BUSP_CLK 13
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#define CLK_GOUT_PERIC0_SPEEDY2_TSP_CLK 14
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#define CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK 15
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#define CLK_GOUT_PERIC0_UART_DBG_EXT_UCLK 16
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#define CLK_GOUT_PERIC0_UART_DBG_PCLK 17
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#define CLK_GOUT_PERIC0_USI00_I_PCLK 18
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#define CLK_GOUT_PERIC0_USI00_I_SCLK_USI 19
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#define CLK_GOUT_PERIC0_USI01_I_PCLK 20
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#define CLK_GOUT_PERIC0_USI01_I_SCLK_USI 21
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#define CLK_GOUT_PERIC0_USI02_I_PCLK 22
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#define CLK_GOUT_PERIC0_USI02_I_SCLK_USI 23
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#define CLK_GOUT_PERIC0_USI03_I_PCLK 24
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#define CLK_GOUT_PERIC0_USI03_I_SCLK_USI 25
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/* CMU_PERIC1 */
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#define CLK_MOUT_PERIC1_BUS_USER 1
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#define CLK_MOUT_PERIC1_SPEEDY2_USER 2
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#define CLK_MOUT_PERIC1_SPI_CAM0_USER 3
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#define CLK_MOUT_PERIC1_SPI_CAM1_USER 4
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#define CLK_MOUT_PERIC1_UART_BT_USER 5
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#define CLK_MOUT_PERIC1_USI04_USER 6
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#define CLK_MOUT_PERIC1_USI05_USER 7
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#define CLK_MOUT_PERIC1_USI06_USER 8
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#define CLK_MOUT_PERIC1_USI07_USER 9
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#define CLK_MOUT_PERIC1_USI08_USER 10
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#define CLK_MOUT_PERIC1_USI09_USER 11
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#define CLK_MOUT_PERIC1_USI10_USER 12
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#define CLK_MOUT_PERIC1_USI11_USER 13
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#define CLK_MOUT_PERIC1_USI12_USER 14
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#define CLK_MOUT_PERIC1_USI13_USER 15
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#define CLK_GOUT_PERIC1_PERIC1_CMU_PERIC1_PCLK 16
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#define CLK_GOUT_PERIC1_RSTNSYNC_CLK_PERIC1_SPEEDY2_CLK 17
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#define CLK_GOUT_PERIC1_AXI2APB_PERIC1P0_ACLK 18
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#define CLK_GOUT_PERIC1_AXI2APB_PERIC1P1_ACLK 19
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#define CLK_GOUT_PERIC1_AXI2APB_PERIC1P2_ACLK 20
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#define CLK_GOUT_PERIC1_GPIO_PERIC1_PCLK 21
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#define CLK_GOUT_PERIC1_HSI2C_CAM0_IPCLK 22
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#define CLK_GOUT_PERIC1_HSI2C_CAM1_IPCLK 23
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#define CLK_GOUT_PERIC1_HSI2C_CAM2_IPCLK 24
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#define CLK_GOUT_PERIC1_HSI2C_CAM3_IPCLK 25
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#define CLK_GOUT_PERIC1_LHM_AXI_P_PERIC1_I_CLK 26
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#define CLK_GOUT_PERIC1_PMU_PERIC1_PCLK 27
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#define CLK_GOUT_PERIC1_RSTNSYNC_CLK_PERIC1_BUSP_CLK 28
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#define CLK_GOUT_PERIC1_SPEEDY2_DDI1_CLK 29
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#define CLK_GOUT_PERIC1_SPEEDY2_DDI1_SCLK 30
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#define CLK_GOUT_PERIC1_SPEEDY2_DDI2_CLK 31
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#define CLK_GOUT_PERIC1_SPEEDY2_DDI2_SCLK 32
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#define CLK_GOUT_PERIC1_SPEEDY2_DDI_CLK 33
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#define CLK_GOUT_PERIC1_SPEEDY2_DDI_SCLK 34
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#define CLK_GOUT_PERIC1_SPEEDY2_TSP1_CLK 35
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#define CLK_GOUT_PERIC1_SPEEDY2_TSP2_CLK 36
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#define CLK_GOUT_PERIC1_SPI_CAM0_PCLK 37
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#define CLK_GOUT_PERIC1_SPI_CAM0_SPI_EXT_CLK 38
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#define CLK_GOUT_PERIC1_SPI_CAM1_PCLK 39
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#define CLK_GOUT_PERIC1_SPI_CAM1_SPI_EXT_CLK 40
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#define CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK 41
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#define CLK_GOUT_PERIC1_UART_BT_EXT_UCLK 42
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#define CLK_GOUT_PERIC1_UART_BT_PCLK 43
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#define CLK_GOUT_PERIC1_USI04_I_PCLK 44
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#define CLK_GOUT_PERIC1_USI04_I_SCLK_USI 45
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#define CLK_GOUT_PERIC1_USI05_I_PCLK 46
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#define CLK_GOUT_PERIC1_USI05_I_SCLK_USI 47
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#define CLK_GOUT_PERIC1_USI06_I_PCLK 48
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#define CLK_GOUT_PERIC1_USI06_I_SCLK_USI 49
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#define CLK_GOUT_PERIC1_USI07_I_PCLK 50
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#define CLK_GOUT_PERIC1_USI07_I_SCLK_USI 51
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#define CLK_GOUT_PERIC1_USI08_I_PCLK 52
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#define CLK_GOUT_PERIC1_USI08_I_SCLK_USI 53
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#define CLK_GOUT_PERIC1_USI09_I_PCLK 54
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#define CLK_GOUT_PERIC1_USI09_I_SCLK_USI 55
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#define CLK_GOUT_PERIC1_USI10_I_PCLK 56
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#define CLK_GOUT_PERIC1_USI10_I_SCLK_USI 57
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#define CLK_GOUT_PERIC1_USI11_I_PCLK 58
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#define CLK_GOUT_PERIC1_USI11_I_SCLK_USI 59
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#define CLK_GOUT_PERIC1_USI12_I_PCLK 60
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#define CLK_GOUT_PERIC1_USI12_I_SCLK_USI 61
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#define CLK_GOUT_PERIC1_USI13_I_PCLK 62
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#define CLK_GOUT_PERIC1_USI13_I_SCLK_USI 63
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#define CLK_GOUT_PERIC1_XIU_P_PERIC1_ACLK 64
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#endif /* _DT_BINDINGS_CLOCK_EXYNOS8895_H */
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