195 lines
6.2 KiB
YAML
195 lines
6.2 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/sound/fsl,ssi.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Freescale Synchronous Serial Interface
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maintainers:
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- Shengjiu Wang <shengjiu.wang@nxp.com>
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description:
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Notes on fsl,playback-dma and fsl,capture-dma
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On SOCs that have an SSI, specific DMA channels are hard-wired for playback
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and capture. On the MPC8610, for example, SSI1 must use DMA channel 0 for
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playback and DMA channel 1 for capture. SSI2 must use DMA channel 2 for
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playback and DMA channel 3 for capture. The developer can choose which
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DMA controller to use, but the channels themselves are hard-wired. The
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purpose of these two properties is to represent this hardware design.
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The device tree nodes for the DMA channels that are referenced by
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"fsl,playback-dma" and "fsl,capture-dma" must be marked as compatible with
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"fsl,ssi-dma-channel". The SOC-specific compatible string (e.g.
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"fsl,mpc8610-dma-channel") can remain. If these nodes are left as
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"fsl,elo-dma-channel" or "fsl,eloplus-dma-channel", then the generic Elo DMA
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drivers (fsldma) will attempt to use them, and it will conflict with the
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sound drivers.
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properties:
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compatible:
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oneOf:
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- items:
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- enum:
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- fsl,imx50-ssi
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- fsl,imx53-ssi
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- const: fsl,imx51-ssi
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- const: fsl,imx21-ssi
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- items:
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- enum:
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- fsl,imx25-ssi
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- fsl,imx27-ssi
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- fsl,imx35-ssi
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- fsl,imx51-ssi
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- const: fsl,imx21-ssi
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- items:
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- enum:
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- fsl,imx6q-ssi
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- fsl,imx6sl-ssi
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- fsl,imx6sx-ssi
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- const: fsl,imx51-ssi
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- items:
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- const: fsl,imx21-ssi
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- items:
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- const: fsl,mpc8610-ssi
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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items:
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- description: The ipg clock for register access
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- description: clock for SSI master mode
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minItems: 1
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clock-names:
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items:
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- const: ipg
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- const: baud
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minItems: 1
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dmas:
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oneOf:
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- items:
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- description: DMA controller phandle and request line for RX
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- description: DMA controller phandle and request line for TX
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- items:
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- description: DMA controller phandle and request line for RX0
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- description: DMA controller phandle and request line for TX0
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- description: DMA controller phandle and request line for RX1
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- description: DMA controller phandle and request line for TX1
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dma-names:
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oneOf:
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- items:
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- const: rx
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- const: tx
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- items:
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- const: rx0
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- const: tx0
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- const: rx1
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- const: tx1
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"#sound-dai-cells":
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const: 0
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description: optional, some dts node didn't add it.
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cell-index:
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [0, 1, 2]
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description: The SSI index
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ac97-gpios:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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description: Please refer to soc-ac97link.txt
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codec-handle:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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Phandle to a 'codec' node that defines an audio
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codec connected to this SSI. This node is typically
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a child of an I2C or other control node.
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fsl,fifo-depth:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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The number of elements in the transmit and receive FIFOs.
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This number is the maximum allowed value for SFCSR[TFWM0].
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enum: [8, 15]
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fsl,fiq-stream-filter:
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type: boolean
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description:
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Disabled DMA and use FIQ instead to filter the codec stream.
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This is necessary for some boards where an incompatible codec
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is connected to this SSI, e.g. on pca100 and pcm043.
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fsl,mode:
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$ref: /schemas/types.yaml#/definitions/string
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enum: [ ac97-slave, ac97-master, i2s-slave, i2s-master,
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lj-slave, lj-master, rj-slave, rj-master ]
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description: |
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"ac97-slave" - AC97 mode, SSI is clock slave
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"ac97-master" - AC97 mode, SSI is clock master
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"i2s-slave" - I2S mode, SSI is clock slave
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"i2s-master" - I2S mode, SSI is clock master
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"lj-slave" - Left justified mode, SSI is clock slave
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"lj-master" - Left justified mode, SSI is clock master
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"rj-slave" - Right justified mode, SSI is clock slave
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"rj-master" - Right justified mode, SSI is clock master
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fsl,ssi-asynchronous:
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type: boolean
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description: If specified, the SSI is to be programmed in asynchronous
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mode. In this mode, pins SRCK, STCK, SRFS, and STFS must
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all be connected to valid signals. In synchronous mode,
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SRCK and SRFS are ignored. Asynchronous mode allows
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playback and capture to use different sample sizes and
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sample rates. Some drivers may require that SRCK and STCK
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be connected together, and SRFS and STFS be connected
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together. This would still allow different sample sizes,
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but not different sample rates.
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fsl,playback-dma:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: Phandle to a node for the DMA channel to use for
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playback of audio. This is typically dictated by SOC
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design. Only used on Power Architecture.
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fsl,capture-dma:
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$ref: /schemas/types.yaml#/definitions/phandle
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description: Phandle to a node for the DMA channel to use for
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capture (recording) of audio. This is typically dictated
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by SOC design. Only used on Power Architecture.
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required:
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- compatible
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- reg
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- interrupts
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- fsl,fifo-depth
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allOf:
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- $ref: dai-common.yaml#
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/imx6qdl-clock.h>
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ssi@2028000 {
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compatible = "fsl,imx6q-ssi", "fsl,imx51-ssi";
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reg = <0x02028000 0x4000>;
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interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6QDL_CLK_SSI1_IPG>,
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<&clks IMX6QDL_CLK_SSI1>;
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clock-names = "ipg", "baud";
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dmas = <&sdma 37 1 0>, <&sdma 38 1 0>;
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dma-names = "rx", "tx";
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#sound-dai-cells = <0>;
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fsl,fifo-depth = <15>;
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};
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