125 lines
3.5 KiB
YAML
125 lines
3.5 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/qcom,qcs615-tlmm.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Technologies, Inc. QCS615 TLMM block
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maintainers:
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- Lijuan Gao <quic_lijuang@quicinc.com>
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description:
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Top Level Mode Multiplexer pin controller in Qualcomm QCS615 SoC.
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allOf:
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- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
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properties:
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compatible:
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const: qcom,qcs615-tlmm
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reg:
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maxItems: 3
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reg-names:
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items:
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- const: east
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- const: west
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- const: south
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interrupts:
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maxItems: 1
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gpio-reserved-ranges:
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minItems: 1
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maxItems: 62
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gpio-line-names:
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maxItems: 123
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patternProperties:
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"-state$":
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oneOf:
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- $ref: "#/$defs/qcom-qcs615-tlmm-state"
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- type: object
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patternProperties:
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"-pins$":
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$ref: "#/$defs/qcom-qcs615-tlmm-state"
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additionalProperties: false
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$defs:
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qcom-qcs615-tlmm-state:
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type: object
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description:
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Pinctrl node's client devices use subnodes for desired pin configuration.
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Client device subnodes use below standard properties.
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$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
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unevaluatedProperties: false
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properties:
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pins:
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description:
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List of gpio pins affected by the properties specified in this
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subnode.
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items:
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oneOf:
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- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-1][0-9]|12[0-2])$"
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- enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk,
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sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]
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minItems: 1
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maxItems: 36
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function:
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description:
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Specify the alternative function to be configured for the specified
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pins.
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enum: [ gpio, adsp_ext, agera_pll, aoss_cti, atest_char, atest_tsens,
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atest_usb, cam_mclk, cci_async, cci_i2c, cci_timer, copy_gp,
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copy_phase, cri_trng, dbg_out_clk, ddr_bist, ddr_pxi, dp_hot,
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edp_hot, edp_lcd, emac_gcc, emac_phy_intr, forced_usb, gcc_gp,
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gp_pdm, gps_tx, hs0_mi2s, hs1_mi2s, jitter_bist, ldo_en,
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ldo_update, m_voc, mclk1, mclk2, mdp_vsync, mdp_vsync0_out,
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mdp_vsync1_out, mdp_vsync2_out, mdp_vsync3_out, mdp_vsync4_out,
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mdp_vsync5_out, mi2s_1, mss_lte, nav_pps_in, nav_pps_out,
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pa_indicator_or, pcie_clk_req, pcie_ep_rst, phase_flag, pll_bist,
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pll_bypassnl, pll_reset_n, prng_rosc, qdss_cti, qdss_gpio,
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qlink_enable, qlink_request, qspi, qup0, qup1, rgmii,
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sd_write_protect, sp_cmu, ter_mi2s, tgu_ch, uim1, uim2, usb0_hs,
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usb1_hs, usb_phy_ps, vfr_1, vsense_trigger_mirnat, wlan, wsa_clk,
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wsa_data ]
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required:
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- pins
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required:
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- compatible
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- reg
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- reg-names
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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tlmm: pinctrl@3000000 {
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compatible = "qcom,qcs615-tlmm";
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reg = <0x03100000 0x300000>,
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<0x03500000 0x300000>,
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<0x03c00000 0x300000>;
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reg-names = "east", "west", "south";
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interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
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gpio-ranges = <&tlmm 0 0 123>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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qup3-uart2-state {
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pins ="gpio16", "gpio17";
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function = "qup0";
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};
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};
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...
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