243 lines
6.1 KiB
C
243 lines
6.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* adq12b.c
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* Driver for MicroAxial ADQ12-B data acquisition and control card
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* written by jeremy theler <thelerg@ib.cnea.gov.ar>
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* instituto balseiro
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* commission nacional de energia atomica
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* universidad nacional de cuyo
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* argentina
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*
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* COMEDI - Linux Control and Measurement Device Interface
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* Copyright (C) 2000 David A. Schleef <ds@schleef.org>
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*/
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/*
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* Driver: adq12b
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* Description: Driver for MicroAxial ADQ12-B data acquisition and control card
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* Devices: [MicroAxial] ADQ12-B (adq12b)
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* Author: jeremy theler <thelerg@ib.cnea.gov.ar>
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* Updated: Thu, 21 Feb 2008 02:56:27 -0300
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* Status: works
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*
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* Configuration options:
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* [0] - I/O base address (set with hardware jumpers)
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* address jumper JADR
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* 0x300 1 (factory default)
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* 0x320 2
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* 0x340 3
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* 0x360 4
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* 0x380 5
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* 0x3A0 6
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* [1] - Analog Input unipolar/bipolar selection
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* selection option JUB
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* bipolar 0 2-3 (factory default)
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* unipolar 1 1-2
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* [2] - Analog Input single-ended/differential selection
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* selection option JCHA JCHB
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* single-ended 0 1-2 1-2 (factory default)
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* differential 1 2-3 2-3
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*
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* Driver for the acquisition card ADQ12-B (without any add-on).
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*
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* - Analog input is subdevice 0 (16 channels single-ended or 8 differential)
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* - Digital input is subdevice 1 (5 channels)
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* - Digital output is subdevice 1 (8 channels)
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* - The PACER is not supported in this version
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*/
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/comedi/comedidev.h>
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/* address scheme (page 2.17 of the manual) */
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#define ADQ12B_CTREG 0x00
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#define ADQ12B_CTREG_MSKP BIT(7) /* enable pacer interrupt */
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#define ADQ12B_CTREG_GTP BIT(6) /* enable pacer */
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#define ADQ12B_CTREG_RANGE(x) ((x) << 4)
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#define ADQ12B_CTREG_CHAN(x) ((x) << 0)
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#define ADQ12B_STINR 0x00
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#define ADQ12B_STINR_OUT2 BIT(7) /* timer 2 output state */
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#define ADQ12B_STINR_OUTP BIT(6) /* pacer output state */
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#define ADQ12B_STINR_EOC BIT(5) /* A/D end-of-conversion */
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#define ADQ12B_STINR_IN_MASK (0x1f << 0)
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#define ADQ12B_OUTBR 0x04
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#define ADQ12B_ADLOW 0x08
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#define ADQ12B_ADHIG 0x09
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#define ADQ12B_TIMER_BASE 0x0c
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/* available ranges through the PGA gains */
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static const struct comedi_lrange range_adq12b_ai_bipolar = {
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4, {
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BIP_RANGE(5),
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BIP_RANGE(2),
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BIP_RANGE(1),
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BIP_RANGE(0.5)
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}
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};
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static const struct comedi_lrange range_adq12b_ai_unipolar = {
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4, {
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UNI_RANGE(5),
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UNI_RANGE(2),
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UNI_RANGE(1),
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UNI_RANGE(0.5)
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}
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};
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struct adq12b_private {
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unsigned int last_ctreg;
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};
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static int adq12b_ai_eoc(struct comedi_device *dev,
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struct comedi_subdevice *s,
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struct comedi_insn *insn,
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unsigned long context)
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{
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unsigned char status;
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status = inb(dev->iobase + ADQ12B_STINR);
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if (status & ADQ12B_STINR_EOC)
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return 0;
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return -EBUSY;
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}
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static int adq12b_ai_insn_read(struct comedi_device *dev,
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struct comedi_subdevice *s,
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struct comedi_insn *insn,
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unsigned int *data)
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{
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struct adq12b_private *devpriv = dev->private;
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unsigned int chan = CR_CHAN(insn->chanspec);
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unsigned int range = CR_RANGE(insn->chanspec);
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unsigned int val;
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int ret;
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int i;
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/* change channel and range only if it is different from the previous */
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val = ADQ12B_CTREG_RANGE(range) | ADQ12B_CTREG_CHAN(chan);
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if (val != devpriv->last_ctreg) {
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outb(val, dev->iobase + ADQ12B_CTREG);
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devpriv->last_ctreg = val;
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usleep_range(50, 100); /* wait for the mux to settle */
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}
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val = inb(dev->iobase + ADQ12B_ADLOW); /* trigger A/D */
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for (i = 0; i < insn->n; i++) {
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ret = comedi_timeout(dev, s, insn, adq12b_ai_eoc, 0);
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if (ret)
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return ret;
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val = inb(dev->iobase + ADQ12B_ADHIG) << 8;
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val |= inb(dev->iobase + ADQ12B_ADLOW); /* retriggers A/D */
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data[i] = val;
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}
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return insn->n;
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}
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static int adq12b_di_insn_bits(struct comedi_device *dev,
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struct comedi_subdevice *s,
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struct comedi_insn *insn, unsigned int *data)
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{
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/* only bits 0-4 have information about digital inputs */
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data[1] = (inb(dev->iobase + ADQ12B_STINR) & ADQ12B_STINR_IN_MASK);
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return insn->n;
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}
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static int adq12b_do_insn_bits(struct comedi_device *dev,
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struct comedi_subdevice *s,
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struct comedi_insn *insn,
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unsigned int *data)
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{
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unsigned int mask;
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unsigned int chan;
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unsigned int val;
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mask = comedi_dio_update_state(s, data);
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if (mask) {
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for (chan = 0; chan < 8; chan++) {
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if ((mask >> chan) & 0x01) {
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val = (s->state >> chan) & 0x01;
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outb((val << 3) | chan,
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dev->iobase + ADQ12B_OUTBR);
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}
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}
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}
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data[1] = s->state;
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return insn->n;
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}
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static int adq12b_attach(struct comedi_device *dev, struct comedi_devconfig *it)
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{
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struct adq12b_private *devpriv;
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struct comedi_subdevice *s;
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int ret;
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ret = comedi_request_region(dev, it->options[0], 0x10);
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if (ret)
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return ret;
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devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
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if (!devpriv)
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return -ENOMEM;
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devpriv->last_ctreg = -1; /* force ctreg update */
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ret = comedi_alloc_subdevices(dev, 3);
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if (ret)
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return ret;
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/* Analog Input subdevice */
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s = &dev->subdevices[0];
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s->type = COMEDI_SUBD_AI;
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if (it->options[2]) {
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s->subdev_flags = SDF_READABLE | SDF_DIFF;
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s->n_chan = 8;
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} else {
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s->subdev_flags = SDF_READABLE | SDF_GROUND;
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s->n_chan = 16;
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}
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s->maxdata = 0xfff;
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s->range_table = it->options[1] ? &range_adq12b_ai_unipolar
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: &range_adq12b_ai_bipolar;
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s->insn_read = adq12b_ai_insn_read;
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/* Digital Input subdevice */
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s = &dev->subdevices[1];
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s->type = COMEDI_SUBD_DI;
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s->subdev_flags = SDF_READABLE;
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s->n_chan = 5;
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s->maxdata = 1;
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s->range_table = &range_digital;
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s->insn_bits = adq12b_di_insn_bits;
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/* Digital Output subdevice */
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s = &dev->subdevices[2];
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s->type = COMEDI_SUBD_DO;
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s->subdev_flags = SDF_WRITABLE;
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s->n_chan = 8;
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s->maxdata = 1;
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s->range_table = &range_digital;
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s->insn_bits = adq12b_do_insn_bits;
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return 0;
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}
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static struct comedi_driver adq12b_driver = {
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.driver_name = "adq12b",
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.module = THIS_MODULE,
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.attach = adq12b_attach,
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.detach = comedi_legacy_detach,
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};
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module_comedi_driver(adq12b_driver);
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MODULE_AUTHOR("Comedi https://www.comedi.org");
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MODULE_DESCRIPTION("Comedi low-level driver");
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MODULE_LICENSE("GPL");
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