1007 lines
26 KiB
C
1007 lines
26 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2018, The Linux Foundation. All rights reserved.
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* Copyright (c) 2024, Danila Tikhonov <danila@jiaxyga.com>
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* Copyright (c) 2024, David Wronek <david@mainlining.org>
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*/
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#include <linux/clk-provider.h>
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <dt-bindings/clock/qcom,sm7150-dispcc.h>
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#include "clk-alpha-pll.h"
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#include "clk-branch.h"
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#include "clk-rcg.h"
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#include "clk-regmap.h"
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#include "clk-regmap-divider.h"
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#include "common.h"
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#include "gdsc.h"
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enum {
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DT_BI_TCXO,
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DT_BI_TCXO_AO,
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DT_GCC_DISP_GPLL0_CLK,
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DT_CHIP_SLEEP_CLK,
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DT_DSI0_PHY_PLL_OUT_BYTECLK,
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DT_DSI0_PHY_PLL_OUT_DSICLK,
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DT_DSI1_PHY_PLL_OUT_BYTECLK,
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DT_DSI1_PHY_PLL_OUT_DSICLK,
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DT_DP_PHY_PLL_LINK_CLK,
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DT_DP_PHY_PLL_VCO_DIV_CLK,
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};
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enum {
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P_BI_TCXO,
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P_CHIP_SLEEP_CLK,
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P_DISPCC_PLL0_OUT_EVEN,
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P_DISPCC_PLL0_OUT_MAIN,
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P_DP_PHY_PLL_LINK_CLK,
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P_DP_PHY_PLL_VCO_DIV_CLK,
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P_DSI0_PHY_PLL_OUT_BYTECLK,
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P_DSI0_PHY_PLL_OUT_DSICLK,
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P_DSI1_PHY_PLL_OUT_BYTECLK,
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P_DSI1_PHY_PLL_OUT_DSICLK,
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P_GCC_DISP_GPLL0_CLK,
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};
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static const struct pll_vco fabia_vco[] = {
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{ 249600000, 2000000000, 0 },
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{ 125000000, 1000000000, 1 },
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};
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/* 860MHz configuration */
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static const struct alpha_pll_config dispcc_pll0_config = {
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.l = 0x2c,
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.alpha = 0xcaaa,
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.test_ctl_val = 0x40000000,
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};
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static struct clk_alpha_pll dispcc_pll0 = {
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.offset = 0x0,
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.vco_table = fabia_vco,
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.num_vco = ARRAY_SIZE(fabia_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
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.clkr = {
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.hw.init = &(const struct clk_init_data) {
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.name = "dispcc_pll0",
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.parent_data = &(const struct clk_parent_data) {
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.index = DT_BI_TCXO,
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_fabia_ops,
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},
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},
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};
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static const struct parent_map dispcc_parent_map_0[] = {
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{ P_BI_TCXO, 0 },
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{ P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
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{ P_DSI1_PHY_PLL_OUT_BYTECLK, 2 },
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};
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static const struct clk_parent_data dispcc_parent_data_0[] = {
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{ .index = DT_BI_TCXO },
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{ .index = DT_DSI0_PHY_PLL_OUT_BYTECLK },
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{ .index = DT_DSI1_PHY_PLL_OUT_BYTECLK },
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};
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static const struct parent_map dispcc_parent_map_1[] = {
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{ P_BI_TCXO, 0 },
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{ P_DP_PHY_PLL_LINK_CLK, 1 },
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{ P_DP_PHY_PLL_VCO_DIV_CLK, 2 },
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};
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static const struct clk_parent_data dispcc_parent_data_1[] = {
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{ .index = DT_BI_TCXO },
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{ .index = DT_DP_PHY_PLL_LINK_CLK },
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{ .index = DT_DP_PHY_PLL_VCO_DIV_CLK },
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};
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static const struct parent_map dispcc_parent_map_2[] = {
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{ P_BI_TCXO, 0 },
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};
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static const struct clk_parent_data dispcc_parent_data_2[] = {
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{ .index = DT_BI_TCXO },
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};
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static const struct clk_parent_data dispcc_parent_data_2_ao[] = {
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{ .index = DT_BI_TCXO_AO },
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};
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static const struct parent_map dispcc_parent_map_3[] = {
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{ P_BI_TCXO, 0 },
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{ P_DISPCC_PLL0_OUT_MAIN, 1 },
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{ P_GCC_DISP_GPLL0_CLK, 4 },
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{ P_DISPCC_PLL0_OUT_EVEN, 5 },
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};
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static const struct clk_parent_data dispcc_parent_data_3[] = {
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{ .index = DT_BI_TCXO },
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{ .hw = &dispcc_pll0.clkr.hw },
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{ .index = DT_GCC_DISP_GPLL0_CLK },
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{ .hw = &dispcc_pll0.clkr.hw },
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};
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static const struct parent_map dispcc_parent_map_4[] = {
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{ P_BI_TCXO, 0 },
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{ P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
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{ P_DSI1_PHY_PLL_OUT_DSICLK, 2 },
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};
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static const struct clk_parent_data dispcc_parent_data_4[] = {
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{ .index = DT_BI_TCXO },
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{ .index = DT_DSI0_PHY_PLL_OUT_DSICLK },
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{ .index = DT_DSI1_PHY_PLL_OUT_DSICLK },
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};
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static const struct parent_map dispcc_parent_map_5[] = {
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{ P_BI_TCXO, 0 },
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{ P_GCC_DISP_GPLL0_CLK, 4 },
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};
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static const struct clk_parent_data dispcc_parent_data_5[] = {
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{ .index = DT_BI_TCXO },
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{ .index = DT_GCC_DISP_GPLL0_CLK },
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};
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static const struct parent_map dispcc_parent_map_6[] = {
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{ P_CHIP_SLEEP_CLK, 0 },
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};
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static const struct clk_parent_data dispcc_parent_data_6[] = {
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{ .index = DT_CHIP_SLEEP_CLK },
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};
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static const struct freq_tbl ftbl_dispcc_mdss_ahb_clk_src[] = {
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F(19200000, P_BI_TCXO, 1, 0, 0),
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F(37500000, P_GCC_DISP_GPLL0_CLK, 16, 0, 0),
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F(75000000, P_GCC_DISP_GPLL0_CLK, 8, 0, 0),
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{ }
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};
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static struct clk_rcg2 dispcc_mdss_ahb_clk_src = {
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.cmd_rcgr = 0x22bc,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = dispcc_parent_map_5,
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.freq_tbl = ftbl_dispcc_mdss_ahb_clk_src,
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "dispcc_mdss_ahb_clk_src",
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.parent_data = dispcc_parent_data_5,
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.num_parents = ARRAY_SIZE(dispcc_parent_data_5),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_shared_ops,
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},
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};
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static const struct freq_tbl ftbl_dispcc_mdss_byte0_clk_src[] = {
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F(19200000, P_BI_TCXO, 1, 0, 0),
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{ }
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};
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static struct clk_rcg2 dispcc_mdss_byte0_clk_src = {
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.cmd_rcgr = 0x2110,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = dispcc_parent_map_0,
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "dispcc_mdss_byte0_clk_src",
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.parent_data = dispcc_parent_data_0,
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.num_parents = ARRAY_SIZE(dispcc_parent_data_0),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_byte2_ops,
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},
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};
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static struct clk_rcg2 dispcc_mdss_byte1_clk_src = {
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.cmd_rcgr = 0x212c,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = dispcc_parent_map_0,
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "dispcc_mdss_byte1_clk_src",
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.parent_data = dispcc_parent_data_0,
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.num_parents = ARRAY_SIZE(dispcc_parent_data_0),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_byte2_ops,
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},
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};
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static struct clk_rcg2 dispcc_mdss_dp_aux_clk_src = {
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.cmd_rcgr = 0x21dc,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = dispcc_parent_map_2,
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.freq_tbl = ftbl_dispcc_mdss_byte0_clk_src,
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "dispcc_mdss_dp_aux_clk_src",
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.parent_data = dispcc_parent_data_2,
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.num_parents = ARRAY_SIZE(dispcc_parent_data_2),
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.ops = &clk_rcg2_ops,
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},
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};
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static const struct freq_tbl ftbl_dispcc_mdss_dp_crypto_clk_src[] = {
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F(108000, P_DP_PHY_PLL_LINK_CLK, 3, 0, 0),
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F(180000, P_DP_PHY_PLL_LINK_CLK, 3, 0, 0),
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F(360000, P_DP_PHY_PLL_LINK_CLK, 1.5, 0, 0),
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F(540000, P_DP_PHY_PLL_LINK_CLK, 1.5, 0, 0),
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{ }
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};
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static struct clk_rcg2 dispcc_mdss_dp_crypto_clk_src = {
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.cmd_rcgr = 0x2194,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = dispcc_parent_map_1,
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.freq_tbl = ftbl_dispcc_mdss_dp_crypto_clk_src,
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "dispcc_mdss_dp_crypto_clk_src",
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.parent_data = dispcc_parent_data_1,
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.num_parents = ARRAY_SIZE(dispcc_parent_data_1),
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.ops = &clk_rcg2_ops,
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},
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};
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static struct clk_rcg2 dispcc_mdss_dp_link_clk_src = {
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.cmd_rcgr = 0x2178,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = dispcc_parent_map_1,
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "dispcc_mdss_dp_link_clk_src",
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.parent_data = dispcc_parent_data_1,
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.num_parents = ARRAY_SIZE(dispcc_parent_data_1),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_byte2_ops,
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},
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};
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static struct clk_rcg2 dispcc_mdss_dp_pixel1_clk_src = {
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.cmd_rcgr = 0x21c4,
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.mnd_width = 16,
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.hid_width = 5,
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.parent_map = dispcc_parent_map_1,
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "dispcc_mdss_dp_pixel1_clk_src",
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.parent_data = dispcc_parent_data_1,
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.num_parents = ARRAY_SIZE(dispcc_parent_data_1),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_dp_ops,
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},
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};
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static struct clk_rcg2 dispcc_mdss_dp_pixel_clk_src = {
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.cmd_rcgr = 0x21ac,
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.mnd_width = 16,
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.hid_width = 5,
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.parent_map = dispcc_parent_map_1,
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "dispcc_mdss_dp_pixel_clk_src",
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.parent_data = dispcc_parent_data_1,
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.num_parents = ARRAY_SIZE(dispcc_parent_data_1),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_dp_ops,
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},
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};
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static struct clk_rcg2 dispcc_mdss_esc0_clk_src = {
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.cmd_rcgr = 0x2148,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = dispcc_parent_map_0,
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.freq_tbl = ftbl_dispcc_mdss_byte0_clk_src,
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "dispcc_mdss_esc0_clk_src",
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.parent_data = dispcc_parent_data_0,
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.num_parents = ARRAY_SIZE(dispcc_parent_data_0),
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.ops = &clk_rcg2_ops,
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},
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};
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static struct clk_rcg2 dispcc_mdss_esc1_clk_src = {
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.cmd_rcgr = 0x2160,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = dispcc_parent_map_0,
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.freq_tbl = ftbl_dispcc_mdss_byte0_clk_src,
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "dispcc_mdss_esc1_clk_src",
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.parent_data = dispcc_parent_data_0,
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.num_parents = ARRAY_SIZE(dispcc_parent_data_0),
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.ops = &clk_rcg2_ops,
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},
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};
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static const struct freq_tbl ftbl_dispcc_mdss_mdp_clk_src[] = {
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F(19200000, P_BI_TCXO, 1, 0, 0),
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F(85714286, P_GCC_DISP_GPLL0_CLK, 7, 0, 0),
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F(100000000, P_GCC_DISP_GPLL0_CLK, 6, 0, 0),
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F(150000000, P_GCC_DISP_GPLL0_CLK, 4, 0, 0),
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F(172000000, P_DISPCC_PLL0_OUT_MAIN, 5, 0, 0),
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F(200000000, P_GCC_DISP_GPLL0_CLK, 3, 0, 0),
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F(286666667, P_DISPCC_PLL0_OUT_MAIN, 3, 0, 0),
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F(300000000, P_GCC_DISP_GPLL0_CLK, 2, 0, 0),
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F(344000000, P_DISPCC_PLL0_OUT_MAIN, 2.5, 0, 0),
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F(430000000, P_DISPCC_PLL0_OUT_MAIN, 2, 0, 0),
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{ }
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};
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static struct clk_rcg2 dispcc_mdss_mdp_clk_src = {
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.cmd_rcgr = 0x20c8,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = dispcc_parent_map_3,
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.freq_tbl = ftbl_dispcc_mdss_mdp_clk_src,
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "dispcc_mdss_mdp_clk_src",
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.parent_data = dispcc_parent_data_3,
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.num_parents = ARRAY_SIZE(dispcc_parent_data_3),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_shared_ops,
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},
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};
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static struct clk_rcg2 dispcc_mdss_pclk0_clk_src = {
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.cmd_rcgr = 0x2098,
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.mnd_width = 8,
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.hid_width = 5,
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.parent_map = dispcc_parent_map_4,
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "dispcc_mdss_pclk0_clk_src",
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.parent_data = dispcc_parent_data_4,
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.num_parents = ARRAY_SIZE(dispcc_parent_data_4),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_pixel_ops,
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},
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};
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static struct clk_rcg2 dispcc_mdss_pclk1_clk_src = {
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.cmd_rcgr = 0x20b0,
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.mnd_width = 8,
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.hid_width = 5,
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.parent_map = dispcc_parent_map_4,
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "dispcc_mdss_pclk1_clk_src",
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.parent_data = dispcc_parent_data_4,
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.num_parents = ARRAY_SIZE(dispcc_parent_data_4),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_pixel_ops,
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},
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};
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static const struct freq_tbl ftbl_dispcc_mdss_rot_clk_src[] = {
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F(19200000, P_BI_TCXO, 1, 0, 0),
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F(171428571, P_GCC_DISP_GPLL0_CLK, 3.5, 0, 0),
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F(200000000, P_GCC_DISP_GPLL0_CLK, 3, 0, 0),
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F(300000000, P_GCC_DISP_GPLL0_CLK, 2, 0, 0),
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F(344000000, P_DISPCC_PLL0_OUT_MAIN, 2.5, 0, 0),
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F(430000000, P_DISPCC_PLL0_OUT_MAIN, 2, 0, 0),
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{ }
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};
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static struct clk_rcg2 dispcc_mdss_rot_clk_src = {
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.cmd_rcgr = 0x20e0,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = dispcc_parent_map_3,
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.freq_tbl = ftbl_dispcc_mdss_rot_clk_src,
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "dispcc_mdss_rot_clk_src",
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.parent_data = dispcc_parent_data_3,
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.num_parents = ARRAY_SIZE(dispcc_parent_data_3),
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.ops = &clk_rcg2_shared_ops,
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},
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};
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static struct clk_rcg2 dispcc_mdss_vsync_clk_src = {
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.cmd_rcgr = 0x20f8,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = dispcc_parent_map_2,
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.freq_tbl = ftbl_dispcc_mdss_byte0_clk_src,
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "dispcc_mdss_vsync_clk_src",
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.parent_data = dispcc_parent_data_2,
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.num_parents = ARRAY_SIZE(dispcc_parent_data_2),
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.ops = &clk_rcg2_ops,
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},
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};
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static const struct freq_tbl ftbl_dispcc_sleep_clk_src[] = {
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F(32000, P_CHIP_SLEEP_CLK, 1, 0, 0),
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{ }
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};
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static struct clk_rcg2 dispcc_sleep_clk_src = {
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.cmd_rcgr = 0x6060,
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.mnd_width = 0,
|
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.hid_width = 5,
|
|
.parent_map = dispcc_parent_map_6,
|
|
.freq_tbl = ftbl_dispcc_sleep_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data) {
|
|
.name = "dispcc_sleep_clk_src",
|
|
.parent_data = dispcc_parent_data_6,
|
|
.num_parents = ARRAY_SIZE(dispcc_parent_data_6),
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 dispcc_xo_clk_src = {
|
|
.cmd_rcgr = 0x6044,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = dispcc_parent_map_2,
|
|
.freq_tbl = ftbl_dispcc_mdss_byte0_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data) {
|
|
.name = "dispcc_xo_clk_src",
|
|
.parent_data = dispcc_parent_data_2_ao,
|
|
.num_parents = ARRAY_SIZE(dispcc_parent_data_2_ao),
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
};
|
|
|
|
static struct clk_branch dispcc_mdss_ahb_clk = {
|
|
.halt_reg = 0x2080,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x2080,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "dispcc_mdss_ahb_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&dispcc_mdss_ahb_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch dispcc_mdss_byte0_clk = {
|
|
.halt_reg = 0x2028,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x2028,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "dispcc_mdss_byte0_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&dispcc_mdss_byte0_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_regmap_div dispcc_mdss_byte0_div_clk_src = {
|
|
.reg = 0x2128,
|
|
.shift = 0,
|
|
.width = 2,
|
|
.clkr = {
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "dispcc_mdss_byte0_div_clk_src",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&dispcc_mdss_byte0_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.ops = &clk_regmap_div_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch dispcc_mdss_byte0_intf_clk = {
|
|
.halt_reg = 0x202c,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x202c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "dispcc_mdss_byte0_intf_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&dispcc_mdss_byte0_div_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch dispcc_mdss_byte1_clk = {
|
|
.halt_reg = 0x2030,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x2030,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "dispcc_mdss_byte1_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&dispcc_mdss_byte1_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_regmap_div dispcc_mdss_byte1_div_clk_src = {
|
|
.reg = 0x2144,
|
|
.shift = 0,
|
|
.width = 2,
|
|
.clkr = {
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "dispcc_mdss_byte1_div_clk_src",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&dispcc_mdss_byte1_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.ops = &clk_regmap_div_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch dispcc_mdss_byte1_intf_clk = {
|
|
.halt_reg = 0x2034,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x2034,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "dispcc_mdss_byte1_intf_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&dispcc_mdss_byte1_div_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch dispcc_mdss_dp_aux_clk = {
|
|
.halt_reg = 0x2054,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x2054,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "dispcc_mdss_dp_aux_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&dispcc_mdss_dp_aux_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch dispcc_mdss_dp_crypto_clk = {
|
|
.halt_reg = 0x2048,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x2048,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "dispcc_mdss_dp_crypto_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&dispcc_mdss_dp_crypto_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch dispcc_mdss_dp_link_clk = {
|
|
.halt_reg = 0x2040,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x2040,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "dispcc_mdss_dp_link_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&dispcc_mdss_dp_link_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch dispcc_mdss_dp_link_intf_clk = {
|
|
.halt_reg = 0x2044,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x2044,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "dispcc_mdss_dp_link_intf_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&dispcc_mdss_dp_link_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch dispcc_mdss_dp_pixel1_clk = {
|
|
.halt_reg = 0x2050,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x2050,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "dispcc_mdss_dp_pixel1_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&dispcc_mdss_dp_pixel1_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch dispcc_mdss_dp_pixel_clk = {
|
|
.halt_reg = 0x204c,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x204c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "dispcc_mdss_dp_pixel_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&dispcc_mdss_dp_pixel_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch dispcc_mdss_esc0_clk = {
|
|
.halt_reg = 0x2038,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x2038,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "dispcc_mdss_esc0_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&dispcc_mdss_esc0_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch dispcc_mdss_esc1_clk = {
|
|
.halt_reg = 0x203c,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x203c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "dispcc_mdss_esc1_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&dispcc_mdss_esc1_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch dispcc_mdss_mdp_clk = {
|
|
.halt_reg = 0x200c,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x200c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "dispcc_mdss_mdp_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&dispcc_mdss_mdp_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch dispcc_mdss_mdp_lut_clk = {
|
|
.halt_reg = 0x201c,
|
|
.halt_check = BRANCH_VOTED,
|
|
.clkr = {
|
|
.enable_reg = 0x201c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "dispcc_mdss_mdp_lut_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&dispcc_mdss_mdp_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch dispcc_mdss_non_gdsc_ahb_clk = {
|
|
.halt_reg = 0x4004,
|
|
.halt_check = BRANCH_VOTED,
|
|
.clkr = {
|
|
.enable_reg = 0x4004,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "dispcc_mdss_non_gdsc_ahb_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&dispcc_mdss_ahb_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch dispcc_mdss_pclk0_clk = {
|
|
.halt_reg = 0x2004,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x2004,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "dispcc_mdss_pclk0_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&dispcc_mdss_pclk0_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch dispcc_mdss_pclk1_clk = {
|
|
.halt_reg = 0x2008,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x2008,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "dispcc_mdss_pclk1_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&dispcc_mdss_pclk1_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch dispcc_mdss_rot_clk = {
|
|
.halt_reg = 0x2014,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x2014,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "dispcc_mdss_rot_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&dispcc_mdss_rot_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch dispcc_mdss_rscc_ahb_clk = {
|
|
.halt_reg = 0x400c,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x400c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "dispcc_mdss_rscc_ahb_clk",
|
|
.parent_names = (const char *[]) {
|
|
"dispcc_mdss_ahb_clk_src",
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch dispcc_mdss_rscc_vsync_clk = {
|
|
.halt_reg = 0x4008,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x4008,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "dispcc_mdss_rscc_vsync_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&dispcc_mdss_vsync_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch dispcc_mdss_vsync_clk = {
|
|
.halt_reg = 0x2024,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x2024,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "dispcc_mdss_vsync_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&dispcc_mdss_vsync_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch dispcc_sleep_clk = {
|
|
.halt_reg = 0x6078,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x6078,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "dispcc_sleep_clk",
|
|
.parent_names = (const char *[]) {
|
|
"dispcc_sleep_clk_src",
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct gdsc mdss_gdsc = {
|
|
.gdscr = 0x3000,
|
|
.en_rest_wait_val = 0x2,
|
|
.en_few_wait_val = 0x2,
|
|
.clk_dis_wait_val = 0xf,
|
|
.pd = {
|
|
.name = "mdss_gdsc",
|
|
},
|
|
.pwrsts = PWRSTS_OFF_ON,
|
|
.flags = HW_CTRL,
|
|
};
|
|
|
|
static struct clk_regmap *dispcc_sm7150_clocks[] = {
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[DISPCC_MDSS_AHB_CLK] = &dispcc_mdss_ahb_clk.clkr,
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[DISPCC_MDSS_AHB_CLK_SRC] = &dispcc_mdss_ahb_clk_src.clkr,
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[DISPCC_MDSS_BYTE0_CLK] = &dispcc_mdss_byte0_clk.clkr,
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[DISPCC_MDSS_BYTE0_CLK_SRC] = &dispcc_mdss_byte0_clk_src.clkr,
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[DISPCC_MDSS_BYTE0_DIV_CLK_SRC] = &dispcc_mdss_byte0_div_clk_src.clkr,
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[DISPCC_MDSS_BYTE0_INTF_CLK] = &dispcc_mdss_byte0_intf_clk.clkr,
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[DISPCC_MDSS_BYTE1_CLK] = &dispcc_mdss_byte1_clk.clkr,
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[DISPCC_MDSS_BYTE1_CLK_SRC] = &dispcc_mdss_byte1_clk_src.clkr,
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[DISPCC_MDSS_BYTE1_DIV_CLK_SRC] = &dispcc_mdss_byte1_div_clk_src.clkr,
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[DISPCC_MDSS_BYTE1_INTF_CLK] = &dispcc_mdss_byte1_intf_clk.clkr,
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[DISPCC_MDSS_DP_AUX_CLK] = &dispcc_mdss_dp_aux_clk.clkr,
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[DISPCC_MDSS_DP_AUX_CLK_SRC] = &dispcc_mdss_dp_aux_clk_src.clkr,
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[DISPCC_MDSS_DP_CRYPTO_CLK] = &dispcc_mdss_dp_crypto_clk.clkr,
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[DISPCC_MDSS_DP_CRYPTO_CLK_SRC] = &dispcc_mdss_dp_crypto_clk_src.clkr,
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[DISPCC_MDSS_DP_LINK_CLK] = &dispcc_mdss_dp_link_clk.clkr,
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[DISPCC_MDSS_DP_LINK_CLK_SRC] = &dispcc_mdss_dp_link_clk_src.clkr,
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[DISPCC_MDSS_DP_LINK_INTF_CLK] = &dispcc_mdss_dp_link_intf_clk.clkr,
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[DISPCC_MDSS_DP_PIXEL1_CLK] = &dispcc_mdss_dp_pixel1_clk.clkr,
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[DISPCC_MDSS_DP_PIXEL1_CLK_SRC] = &dispcc_mdss_dp_pixel1_clk_src.clkr,
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[DISPCC_MDSS_DP_PIXEL_CLK] = &dispcc_mdss_dp_pixel_clk.clkr,
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[DISPCC_MDSS_DP_PIXEL_CLK_SRC] = &dispcc_mdss_dp_pixel_clk_src.clkr,
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[DISPCC_MDSS_ESC0_CLK] = &dispcc_mdss_esc0_clk.clkr,
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[DISPCC_MDSS_ESC0_CLK_SRC] = &dispcc_mdss_esc0_clk_src.clkr,
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[DISPCC_MDSS_ESC1_CLK] = &dispcc_mdss_esc1_clk.clkr,
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[DISPCC_MDSS_ESC1_CLK_SRC] = &dispcc_mdss_esc1_clk_src.clkr,
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[DISPCC_MDSS_MDP_CLK] = &dispcc_mdss_mdp_clk.clkr,
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[DISPCC_MDSS_MDP_CLK_SRC] = &dispcc_mdss_mdp_clk_src.clkr,
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[DISPCC_MDSS_MDP_LUT_CLK] = &dispcc_mdss_mdp_lut_clk.clkr,
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[DISPCC_MDSS_NON_GDSC_AHB_CLK] = &dispcc_mdss_non_gdsc_ahb_clk.clkr,
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[DISPCC_MDSS_PCLK0_CLK] = &dispcc_mdss_pclk0_clk.clkr,
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[DISPCC_MDSS_PCLK0_CLK_SRC] = &dispcc_mdss_pclk0_clk_src.clkr,
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[DISPCC_MDSS_PCLK1_CLK] = &dispcc_mdss_pclk1_clk.clkr,
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[DISPCC_MDSS_PCLK1_CLK_SRC] = &dispcc_mdss_pclk1_clk_src.clkr,
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[DISPCC_MDSS_ROT_CLK] = &dispcc_mdss_rot_clk.clkr,
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[DISPCC_MDSS_ROT_CLK_SRC] = &dispcc_mdss_rot_clk_src.clkr,
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[DISPCC_MDSS_RSCC_AHB_CLK] = &dispcc_mdss_rscc_ahb_clk.clkr,
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[DISPCC_MDSS_RSCC_VSYNC_CLK] = &dispcc_mdss_rscc_vsync_clk.clkr,
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[DISPCC_MDSS_VSYNC_CLK] = &dispcc_mdss_vsync_clk.clkr,
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[DISPCC_MDSS_VSYNC_CLK_SRC] = &dispcc_mdss_vsync_clk_src.clkr,
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[DISPCC_PLL0] = &dispcc_pll0.clkr,
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[DISPCC_SLEEP_CLK] = &dispcc_sleep_clk.clkr,
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[DISPCC_SLEEP_CLK_SRC] = &dispcc_sleep_clk_src.clkr,
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[DISPCC_XO_CLK_SRC] = &dispcc_xo_clk_src.clkr,
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};
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static struct gdsc *dispcc_sm7150_gdscs[] = {
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[MDSS_GDSC] = &mdss_gdsc,
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};
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static const struct regmap_config dispcc_sm7150_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = 0x10000,
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.fast_io = true,
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};
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static const struct qcom_cc_desc dispcc_sm7150_desc = {
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.config = &dispcc_sm7150_regmap_config,
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.clks = dispcc_sm7150_clocks,
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.num_clks = ARRAY_SIZE(dispcc_sm7150_clocks),
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.gdscs = dispcc_sm7150_gdscs,
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.num_gdscs = ARRAY_SIZE(dispcc_sm7150_gdscs),
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};
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static const struct of_device_id dispcc_sm7150_match_table[] = {
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{ .compatible = "qcom,sm7150-dispcc" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, dispcc_sm7150_match_table);
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static int dispcc_sm7150_probe(struct platform_device *pdev)
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{
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struct regmap *regmap;
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regmap = qcom_cc_map(pdev, &dispcc_sm7150_desc);
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if (IS_ERR(regmap))
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return PTR_ERR(regmap);
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clk_fabia_pll_configure(&dispcc_pll0, regmap, &dispcc_pll0_config);
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/* Enable clock gating for DSI and MDP clocks */
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regmap_update_bits(regmap, 0x8000, 0x7f0, 0x7f0);
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/* Keep some clocks always-on */
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qcom_branch_set_clk_en(regmap, 0x605c); /* DISPCC_XO_CLK */
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return qcom_cc_really_probe(&pdev->dev, &dispcc_sm7150_desc, regmap);
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}
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static struct platform_driver dispcc_sm7150_driver = {
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.probe = dispcc_sm7150_probe,
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.driver = {
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.name = "dispcc-sm7150",
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.of_match_table = dispcc_sm7150_match_table,
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},
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};
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module_platform_driver(dispcc_sm7150_driver);
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MODULE_DESCRIPTION("Qualcomm SM7150 Display Clock Controller");
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MODULE_LICENSE("GPL");
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