1869 lines
48 KiB
C
1869 lines
48 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/mod_devicetable.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <dt-bindings/clock/qcom,sa8775p-camcc.h>
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#include "clk-alpha-pll.h"
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#include "clk-branch.h"
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#include "clk-pll.h"
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#include "clk-rcg.h"
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#include "clk-regmap.h"
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#include "clk-regmap-divider.h"
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#include "clk-regmap-mux.h"
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#include "common.h"
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#include "gdsc.h"
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#include "reset.h"
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enum {
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DT_IFACE,
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DT_BI_TCXO,
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DT_BI_TCXO_AO,
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DT_SLEEP_CLK,
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};
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enum {
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P_BI_TCXO,
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P_BI_TCXO_AO,
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P_CAM_CC_PLL0_OUT_EVEN,
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P_CAM_CC_PLL0_OUT_MAIN,
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P_CAM_CC_PLL0_OUT_ODD,
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P_CAM_CC_PLL2_OUT_EVEN,
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P_CAM_CC_PLL2_OUT_MAIN,
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P_CAM_CC_PLL3_OUT_EVEN,
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P_CAM_CC_PLL4_OUT_EVEN,
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P_CAM_CC_PLL5_OUT_EVEN,
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P_SLEEP_CLK,
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};
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static const struct pll_vco lucid_evo_vco[] = {
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{ 249600000, 2020000000, 0 },
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};
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static const struct pll_vco rivian_evo_vco[] = {
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{ 864000000, 1056000000, 0 },
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};
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static const struct alpha_pll_config cam_cc_pll0_config = {
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.l = 0x3e,
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.alpha = 0x8000,
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.config_ctl_val = 0x20485699,
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.config_ctl_hi_val = 0x00182261,
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.config_ctl_hi1_val = 0x32aa299c,
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.user_ctl_val = 0x00008400,
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.user_ctl_hi_val = 0x00400805,
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};
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static struct clk_alpha_pll cam_cc_pll0 = {
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.offset = 0x0,
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.vco_table = lucid_evo_vco,
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.num_vco = ARRAY_SIZE(lucid_evo_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
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.clkr = {
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.hw.init = &(const struct clk_init_data) {
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.name = "cam_cc_pll0",
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.parent_data = &(const struct clk_parent_data) {
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.index = DT_BI_TCXO,
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_lucid_evo_ops,
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},
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},
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};
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static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = {
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{ 0x1, 2 },
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{ }
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};
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static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = {
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.offset = 0x0,
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.post_div_shift = 10,
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.post_div_table = post_div_table_cam_cc_pll0_out_even,
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.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_even),
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.width = 4,
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "cam_cc_pll0_out_even",
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.parent_hws = (const struct clk_hw*[]) {
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&cam_cc_pll0.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
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},
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};
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static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] = {
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{ 0x2, 3 },
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{ }
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};
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static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = {
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.offset = 0x0,
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.post_div_shift = 14,
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.post_div_table = post_div_table_cam_cc_pll0_out_odd,
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.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll0_out_odd),
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.width = 4,
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "cam_cc_pll0_out_odd",
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.parent_hws = (const struct clk_hw*[]) {
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&cam_cc_pll0.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
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},
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};
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static const struct alpha_pll_config cam_cc_pll2_config = {
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.l = 0x32,
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.alpha = 0x0,
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.config_ctl_val = 0x90008820,
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.config_ctl_hi_val = 0x00890263,
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.config_ctl_hi1_val = 0x00000247,
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.user_ctl_val = 0x00000000,
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.user_ctl_hi_val = 0x00400000,
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};
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static struct clk_alpha_pll cam_cc_pll2 = {
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.offset = 0x1000,
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.vco_table = rivian_evo_vco,
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.num_vco = ARRAY_SIZE(rivian_evo_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_RIVIAN_EVO],
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.clkr = {
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.hw.init = &(const struct clk_init_data) {
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.name = "cam_cc_pll2",
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.parent_data = &(const struct clk_parent_data) {
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.index = DT_BI_TCXO,
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_rivian_evo_ops,
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},
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},
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};
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static const struct alpha_pll_config cam_cc_pll3_config = {
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.l = 0x32,
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.alpha = 0x0,
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.config_ctl_val = 0x20485699,
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.config_ctl_hi_val = 0x00182261,
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.config_ctl_hi1_val = 0x32aa299c,
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.user_ctl_val = 0x00000400,
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.user_ctl_hi_val = 0x00400805,
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};
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static struct clk_alpha_pll cam_cc_pll3 = {
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.offset = 0x2000,
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.vco_table = lucid_evo_vco,
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.num_vco = ARRAY_SIZE(lucid_evo_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
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.clkr = {
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.hw.init = &(const struct clk_init_data) {
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.name = "cam_cc_pll3",
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.parent_data = &(const struct clk_parent_data) {
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.index = DT_BI_TCXO,
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_lucid_evo_ops,
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},
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},
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};
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static const struct clk_div_table post_div_table_cam_cc_pll3_out_even[] = {
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{ 0x1, 2 },
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{ }
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};
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static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = {
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.offset = 0x2000,
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.post_div_shift = 10,
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.post_div_table = post_div_table_cam_cc_pll3_out_even,
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.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll3_out_even),
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.width = 4,
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "cam_cc_pll3_out_even",
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.parent_hws = (const struct clk_hw*[]) {
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&cam_cc_pll3.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
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},
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};
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static const struct alpha_pll_config cam_cc_pll4_config = {
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.l = 0x32,
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.alpha = 0x0,
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.config_ctl_val = 0x20485699,
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.config_ctl_hi_val = 0x00182261,
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.config_ctl_hi1_val = 0x32aa299c,
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.user_ctl_val = 0x00000400,
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.user_ctl_hi_val = 0x00400805,
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};
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static struct clk_alpha_pll cam_cc_pll4 = {
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.offset = 0x3000,
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.vco_table = lucid_evo_vco,
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.num_vco = ARRAY_SIZE(lucid_evo_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
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.clkr = {
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.hw.init = &(const struct clk_init_data) {
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.name = "cam_cc_pll4",
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.parent_data = &(const struct clk_parent_data) {
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.index = DT_BI_TCXO,
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_lucid_evo_ops,
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},
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},
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};
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static const struct clk_div_table post_div_table_cam_cc_pll4_out_even[] = {
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{ 0x1, 2 },
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{ }
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};
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static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = {
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.offset = 0x3000,
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.post_div_shift = 10,
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.post_div_table = post_div_table_cam_cc_pll4_out_even,
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.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll4_out_even),
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.width = 4,
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "cam_cc_pll4_out_even",
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.parent_hws = (const struct clk_hw*[]) {
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&cam_cc_pll4.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
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},
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};
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static const struct alpha_pll_config cam_cc_pll5_config = {
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.l = 0x32,
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.alpha = 0x0,
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.config_ctl_val = 0x20485699,
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.config_ctl_hi_val = 0x00182261,
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.config_ctl_hi1_val = 0x32aa299c,
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.user_ctl_val = 0x00000400,
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.user_ctl_hi_val = 0x00400805,
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};
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static struct clk_alpha_pll cam_cc_pll5 = {
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.offset = 0x4000,
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.vco_table = lucid_evo_vco,
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.num_vco = ARRAY_SIZE(lucid_evo_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
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.clkr = {
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.hw.init = &(const struct clk_init_data) {
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.name = "cam_cc_pll5",
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.parent_data = &(const struct clk_parent_data) {
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.index = DT_BI_TCXO,
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_lucid_evo_ops,
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},
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},
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};
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static const struct clk_div_table post_div_table_cam_cc_pll5_out_even[] = {
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{ 0x1, 2 },
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{ }
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};
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static struct clk_alpha_pll_postdiv cam_cc_pll5_out_even = {
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.offset = 0x4000,
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.post_div_shift = 10,
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.post_div_table = post_div_table_cam_cc_pll5_out_even,
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.num_post_div = ARRAY_SIZE(post_div_table_cam_cc_pll5_out_even),
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.width = 4,
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "cam_cc_pll5_out_even",
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.parent_hws = (const struct clk_hw*[]) {
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&cam_cc_pll5.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_alpha_pll_postdiv_lucid_evo_ops,
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},
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};
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static const struct parent_map cam_cc_parent_map_0[] = {
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{ P_BI_TCXO, 0 },
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{ P_CAM_CC_PLL0_OUT_MAIN, 1 },
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{ P_CAM_CC_PLL0_OUT_EVEN, 2 },
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{ P_CAM_CC_PLL0_OUT_ODD, 3 },
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};
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static const struct clk_parent_data cam_cc_parent_data_0[] = {
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{ .index = DT_BI_TCXO },
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{ .hw = &cam_cc_pll0.clkr.hw },
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{ .hw = &cam_cc_pll0_out_even.clkr.hw },
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{ .hw = &cam_cc_pll0_out_odd.clkr.hw },
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};
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static const struct parent_map cam_cc_parent_map_1[] = {
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{ P_BI_TCXO, 0 },
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{ P_CAM_CC_PLL2_OUT_EVEN, 3 },
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{ P_CAM_CC_PLL2_OUT_MAIN, 5 },
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};
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static const struct clk_parent_data cam_cc_parent_data_1[] = {
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{ .index = DT_BI_TCXO },
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{ .hw = &cam_cc_pll2.clkr.hw },
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{ .hw = &cam_cc_pll2.clkr.hw },
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};
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static const struct parent_map cam_cc_parent_map_2[] = {
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{ P_BI_TCXO, 0 },
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{ P_CAM_CC_PLL4_OUT_EVEN, 6 },
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};
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static const struct clk_parent_data cam_cc_parent_data_2[] = {
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{ .index = DT_BI_TCXO },
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{ .hw = &cam_cc_pll4_out_even.clkr.hw },
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};
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static const struct parent_map cam_cc_parent_map_3[] = {
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{ P_BI_TCXO, 0 },
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{ P_CAM_CC_PLL5_OUT_EVEN, 6 },
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};
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static const struct clk_parent_data cam_cc_parent_data_3[] = {
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{ .index = DT_BI_TCXO },
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{ .hw = &cam_cc_pll5_out_even.clkr.hw },
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};
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static const struct parent_map cam_cc_parent_map_4[] = {
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{ P_BI_TCXO, 0 },
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{ P_CAM_CC_PLL3_OUT_EVEN, 6 },
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};
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static const struct clk_parent_data cam_cc_parent_data_4[] = {
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{ .index = DT_BI_TCXO },
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{ .hw = &cam_cc_pll3_out_even.clkr.hw },
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};
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static const struct parent_map cam_cc_parent_map_5[] = {
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{ P_SLEEP_CLK, 0 },
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};
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static const struct clk_parent_data cam_cc_parent_data_5[] = {
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{ .index = DT_SLEEP_CLK },
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};
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static const struct parent_map cam_cc_parent_map_6_ao[] = {
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{ P_BI_TCXO_AO, 0 },
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};
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static const struct clk_parent_data cam_cc_parent_data_6_ao[] = {
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{ .index = DT_BI_TCXO_AO },
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};
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static const struct freq_tbl ftbl_cam_cc_camnoc_axi_clk_src[] = {
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F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
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{ }
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};
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static struct clk_rcg2 cam_cc_camnoc_axi_clk_src = {
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.cmd_rcgr = 0x13170,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = cam_cc_parent_map_0,
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.freq_tbl = ftbl_cam_cc_camnoc_axi_clk_src,
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "cam_cc_camnoc_axi_clk_src",
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.parent_data = cam_cc_parent_data_0,
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.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_shared_ops,
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},
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};
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static const struct freq_tbl ftbl_cam_cc_cci_0_clk_src[] = {
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F(37500000, P_CAM_CC_PLL0_OUT_MAIN, 16, 1, 2),
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{ }
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};
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static struct clk_rcg2 cam_cc_cci_0_clk_src = {
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.cmd_rcgr = 0x130a0,
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.mnd_width = 8,
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.hid_width = 5,
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.parent_map = cam_cc_parent_map_0,
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.freq_tbl = ftbl_cam_cc_cci_0_clk_src,
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "cam_cc_cci_0_clk_src",
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.parent_data = cam_cc_parent_data_0,
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.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_shared_ops,
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},
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};
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static struct clk_rcg2 cam_cc_cci_1_clk_src = {
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.cmd_rcgr = 0x130bc,
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.mnd_width = 8,
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.hid_width = 5,
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.parent_map = cam_cc_parent_map_0,
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.freq_tbl = ftbl_cam_cc_cci_0_clk_src,
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "cam_cc_cci_1_clk_src",
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.parent_data = cam_cc_parent_data_0,
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.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_shared_ops,
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},
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};
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static struct clk_rcg2 cam_cc_cci_2_clk_src = {
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.cmd_rcgr = 0x130d8,
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.mnd_width = 8,
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.hid_width = 5,
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.parent_map = cam_cc_parent_map_0,
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.freq_tbl = ftbl_cam_cc_cci_0_clk_src,
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "cam_cc_cci_2_clk_src",
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.parent_data = cam_cc_parent_data_0,
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.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
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.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_rcg2_shared_ops,
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 cam_cc_cci_3_clk_src = {
|
|
.cmd_rcgr = 0x130f4,
|
|
.mnd_width = 8,
|
|
.hid_width = 5,
|
|
.parent_map = cam_cc_parent_map_0,
|
|
.freq_tbl = ftbl_cam_cc_cci_0_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_cci_3_clk_src",
|
|
.parent_data = cam_cc_parent_data_0,
|
|
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_rcg2_shared_ops,
|
|
},
|
|
};
|
|
|
|
static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = {
|
|
F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0),
|
|
{ }
|
|
};
|
|
|
|
static struct clk_rcg2 cam_cc_cphy_rx_clk_src = {
|
|
.cmd_rcgr = 0x11034,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = cam_cc_parent_map_0,
|
|
.freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_cphy_rx_clk_src",
|
|
.parent_data = cam_cc_parent_data_0,
|
|
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_rcg2_shared_ops,
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 cam_cc_csi0phytimer_clk_src = {
|
|
.cmd_rcgr = 0x15074,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = cam_cc_parent_map_0,
|
|
.freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_csi0phytimer_clk_src",
|
|
.parent_data = cam_cc_parent_data_0,
|
|
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_rcg2_shared_ops,
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 cam_cc_csi1phytimer_clk_src = {
|
|
.cmd_rcgr = 0x15098,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = cam_cc_parent_map_0,
|
|
.freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_csi1phytimer_clk_src",
|
|
.parent_data = cam_cc_parent_data_0,
|
|
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_rcg2_shared_ops,
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 cam_cc_csi2phytimer_clk_src = {
|
|
.cmd_rcgr = 0x150b8,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = cam_cc_parent_map_0,
|
|
.freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_csi2phytimer_clk_src",
|
|
.parent_data = cam_cc_parent_data_0,
|
|
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_rcg2_shared_ops,
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 cam_cc_csi3phytimer_clk_src = {
|
|
.cmd_rcgr = 0x150d8,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = cam_cc_parent_map_0,
|
|
.freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_csi3phytimer_clk_src",
|
|
.parent_data = cam_cc_parent_data_0,
|
|
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_rcg2_shared_ops,
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 cam_cc_csid_clk_src = {
|
|
.cmd_rcgr = 0x13150,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = cam_cc_parent_map_0,
|
|
.freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_csid_clk_src",
|
|
.parent_data = cam_cc_parent_data_0,
|
|
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_rcg2_shared_ops,
|
|
},
|
|
};
|
|
|
|
static const struct freq_tbl ftbl_cam_cc_fast_ahb_clk_src[] = {
|
|
F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0),
|
|
F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
|
|
{ }
|
|
};
|
|
|
|
static struct clk_rcg2 cam_cc_fast_ahb_clk_src = {
|
|
.cmd_rcgr = 0x13120,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = cam_cc_parent_map_0,
|
|
.freq_tbl = ftbl_cam_cc_fast_ahb_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_fast_ahb_clk_src",
|
|
.parent_data = cam_cc_parent_data_0,
|
|
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_rcg2_shared_ops,
|
|
},
|
|
};
|
|
|
|
static const struct freq_tbl ftbl_cam_cc_icp_clk_src[] = {
|
|
F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
|
|
F(600000000, P_CAM_CC_PLL0_OUT_MAIN, 2, 0, 0),
|
|
{ }
|
|
};
|
|
|
|
static struct clk_rcg2 cam_cc_icp_clk_src = {
|
|
.cmd_rcgr = 0x1307c,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = cam_cc_parent_map_0,
|
|
.freq_tbl = ftbl_cam_cc_icp_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_icp_clk_src",
|
|
.parent_data = cam_cc_parent_data_0,
|
|
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_rcg2_shared_ops,
|
|
},
|
|
};
|
|
|
|
static const struct freq_tbl ftbl_cam_cc_ife_0_clk_src[] = {
|
|
F(480000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
|
|
F(600000000, P_CAM_CC_PLL4_OUT_EVEN, 1, 0, 0),
|
|
{ }
|
|
};
|
|
|
|
static struct clk_rcg2 cam_cc_ife_0_clk_src = {
|
|
.cmd_rcgr = 0x11004,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = cam_cc_parent_map_2,
|
|
.freq_tbl = ftbl_cam_cc_ife_0_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_ife_0_clk_src",
|
|
.parent_data = cam_cc_parent_data_2,
|
|
.num_parents = ARRAY_SIZE(cam_cc_parent_data_2),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_rcg2_shared_ops,
|
|
},
|
|
};
|
|
|
|
static const struct freq_tbl ftbl_cam_cc_ife_1_clk_src[] = {
|
|
F(480000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
|
|
F(600000000, P_CAM_CC_PLL5_OUT_EVEN, 1, 0, 0),
|
|
{ }
|
|
};
|
|
|
|
static struct clk_rcg2 cam_cc_ife_1_clk_src = {
|
|
.cmd_rcgr = 0x12004,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = cam_cc_parent_map_3,
|
|
.freq_tbl = ftbl_cam_cc_ife_1_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_ife_1_clk_src",
|
|
.parent_data = cam_cc_parent_data_3,
|
|
.num_parents = ARRAY_SIZE(cam_cc_parent_data_3),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_rcg2_shared_ops,
|
|
},
|
|
};
|
|
|
|
static const struct freq_tbl ftbl_cam_cc_ife_lite_clk_src[] = {
|
|
F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0),
|
|
F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0),
|
|
{ }
|
|
};
|
|
|
|
static struct clk_rcg2 cam_cc_ife_lite_clk_src = {
|
|
.cmd_rcgr = 0x13000,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = cam_cc_parent_map_0,
|
|
.freq_tbl = ftbl_cam_cc_ife_lite_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_ife_lite_clk_src",
|
|
.parent_data = cam_cc_parent_data_0,
|
|
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_rcg2_shared_ops,
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = {
|
|
.cmd_rcgr = 0x13020,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = cam_cc_parent_map_0,
|
|
.freq_tbl = ftbl_cam_cc_cphy_rx_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_ife_lite_csid_clk_src",
|
|
.parent_data = cam_cc_parent_data_0,
|
|
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_rcg2_shared_ops,
|
|
},
|
|
};
|
|
|
|
static const struct freq_tbl ftbl_cam_cc_ipe_clk_src[] = {
|
|
F(480000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
|
|
F(600000000, P_CAM_CC_PLL3_OUT_EVEN, 1, 0, 0),
|
|
{ }
|
|
};
|
|
|
|
static struct clk_rcg2 cam_cc_ipe_clk_src = {
|
|
.cmd_rcgr = 0x10004,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = cam_cc_parent_map_4,
|
|
.freq_tbl = ftbl_cam_cc_ipe_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_ipe_clk_src",
|
|
.parent_data = cam_cc_parent_data_4,
|
|
.num_parents = ARRAY_SIZE(cam_cc_parent_data_4),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_rcg2_shared_ops,
|
|
},
|
|
};
|
|
|
|
static const struct freq_tbl ftbl_cam_cc_mclk0_clk_src[] = {
|
|
F(19200000, P_CAM_CC_PLL2_OUT_MAIN, 1, 1, 50),
|
|
F(24000000, P_CAM_CC_PLL2_OUT_MAIN, 10, 1, 4),
|
|
F(64000000, P_CAM_CC_PLL2_OUT_MAIN, 15, 0, 0),
|
|
{ }
|
|
};
|
|
|
|
static struct clk_rcg2 cam_cc_mclk0_clk_src = {
|
|
.cmd_rcgr = 0x15004,
|
|
.mnd_width = 8,
|
|
.hid_width = 5,
|
|
.parent_map = cam_cc_parent_map_1,
|
|
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_mclk0_clk_src",
|
|
.parent_data = cam_cc_parent_data_1,
|
|
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_rcg2_shared_ops,
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 cam_cc_mclk1_clk_src = {
|
|
.cmd_rcgr = 0x15020,
|
|
.mnd_width = 8,
|
|
.hid_width = 5,
|
|
.parent_map = cam_cc_parent_map_1,
|
|
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_mclk1_clk_src",
|
|
.parent_data = cam_cc_parent_data_1,
|
|
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_rcg2_shared_ops,
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 cam_cc_mclk2_clk_src = {
|
|
.cmd_rcgr = 0x1503c,
|
|
.mnd_width = 8,
|
|
.hid_width = 5,
|
|
.parent_map = cam_cc_parent_map_1,
|
|
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_mclk2_clk_src",
|
|
.parent_data = cam_cc_parent_data_1,
|
|
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_rcg2_shared_ops,
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 cam_cc_mclk3_clk_src = {
|
|
.cmd_rcgr = 0x15058,
|
|
.mnd_width = 8,
|
|
.hid_width = 5,
|
|
.parent_map = cam_cc_parent_map_1,
|
|
.freq_tbl = ftbl_cam_cc_mclk0_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_mclk3_clk_src",
|
|
.parent_data = cam_cc_parent_data_1,
|
|
.num_parents = ARRAY_SIZE(cam_cc_parent_data_1),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_rcg2_shared_ops,
|
|
},
|
|
};
|
|
|
|
static const struct freq_tbl ftbl_cam_cc_sleep_clk_src[] = {
|
|
F(32000, P_SLEEP_CLK, 1, 0, 0),
|
|
{ }
|
|
};
|
|
|
|
static struct clk_rcg2 cam_cc_sleep_clk_src = {
|
|
.cmd_rcgr = 0x131f0,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = cam_cc_parent_map_5,
|
|
.freq_tbl = ftbl_cam_cc_sleep_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_sleep_clk_src",
|
|
.parent_data = cam_cc_parent_data_5,
|
|
.num_parents = ARRAY_SIZE(cam_cc_parent_data_5),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_rcg2_shared_ops,
|
|
},
|
|
};
|
|
|
|
static const struct freq_tbl ftbl_cam_cc_slow_ahb_clk_src[] = {
|
|
F(80000000, P_CAM_CC_PLL0_OUT_EVEN, 7.5, 0, 0),
|
|
{ }
|
|
};
|
|
|
|
static struct clk_rcg2 cam_cc_slow_ahb_clk_src = {
|
|
.cmd_rcgr = 0x13138,
|
|
.mnd_width = 8,
|
|
.hid_width = 5,
|
|
.parent_map = cam_cc_parent_map_0,
|
|
.freq_tbl = ftbl_cam_cc_slow_ahb_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_slow_ahb_clk_src",
|
|
.parent_data = cam_cc_parent_data_0,
|
|
.num_parents = ARRAY_SIZE(cam_cc_parent_data_0),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_rcg2_shared_ops,
|
|
},
|
|
};
|
|
|
|
static const struct freq_tbl ftbl_cam_cc_xo_clk_src[] = {
|
|
F(19200000, P_BI_TCXO_AO, 1, 0, 0),
|
|
{ }
|
|
};
|
|
|
|
static struct clk_rcg2 cam_cc_xo_clk_src = {
|
|
.cmd_rcgr = 0x131d4,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = cam_cc_parent_map_6_ao,
|
|
.freq_tbl = ftbl_cam_cc_xo_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_xo_clk_src",
|
|
.parent_data = cam_cc_parent_data_6_ao,
|
|
.num_parents = ARRAY_SIZE(cam_cc_parent_data_6_ao),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_rcg2_shared_ops,
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_camnoc_axi_clk = {
|
|
.halt_reg = 0x13188,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x13188,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_camnoc_axi_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&cam_cc_camnoc_axi_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_camnoc_dcd_xo_clk = {
|
|
.halt_reg = 0x13190,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x13190,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_camnoc_dcd_xo_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&cam_cc_xo_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_qdss_debug_xo_clk = {
|
|
.halt_reg = 0x131b8,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x131b8,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_qdss_debug_xo_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&cam_cc_xo_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_cci_0_clk = {
|
|
.halt_reg = 0x130b8,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x130b8,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_cci_0_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&cam_cc_cci_0_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_cci_1_clk = {
|
|
.halt_reg = 0x130d4,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x130d4,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_cci_1_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&cam_cc_cci_1_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_cci_2_clk = {
|
|
.halt_reg = 0x130f0,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x130f0,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_cci_2_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&cam_cc_cci_2_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_cci_3_clk = {
|
|
.halt_reg = 0x1310c,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x1310c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_cci_3_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&cam_cc_cci_3_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_core_ahb_clk = {
|
|
.halt_reg = 0x131d0,
|
|
.halt_check = BRANCH_HALT_DELAY,
|
|
.clkr = {
|
|
.enable_reg = 0x131d0,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_core_ahb_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&cam_cc_slow_ahb_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_cpas_ahb_clk = {
|
|
.halt_reg = 0x13110,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x13110,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_cpas_ahb_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&cam_cc_slow_ahb_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_cpas_fast_ahb_clk = {
|
|
.halt_reg = 0x13118,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x13118,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_cpas_fast_ahb_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&cam_cc_fast_ahb_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_cpas_ife_0_clk = {
|
|
.halt_reg = 0x11024,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x11024,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_cpas_ife_0_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&cam_cc_ife_0_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_cpas_ife_1_clk = {
|
|
.halt_reg = 0x12024,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x12024,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_cpas_ife_1_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&cam_cc_ife_1_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_cpas_ife_lite_clk = {
|
|
.halt_reg = 0x1301c,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x1301c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_cpas_ife_lite_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&cam_cc_ife_lite_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_cpas_ipe_clk = {
|
|
.halt_reg = 0x10024,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x10024,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_cpas_ipe_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&cam_cc_ipe_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_cpas_sfe_lite_0_clk = {
|
|
.halt_reg = 0x13050,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x13050,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_cpas_sfe_lite_0_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&cam_cc_ife_0_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_cpas_sfe_lite_1_clk = {
|
|
.halt_reg = 0x13068,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x13068,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_cpas_sfe_lite_1_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&cam_cc_ife_1_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_csi0phytimer_clk = {
|
|
.halt_reg = 0x1508c,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x1508c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_csi0phytimer_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&cam_cc_csi0phytimer_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_csi1phytimer_clk = {
|
|
.halt_reg = 0x150b0,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x150b0,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_csi1phytimer_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&cam_cc_csi1phytimer_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_csi2phytimer_clk = {
|
|
.halt_reg = 0x150d0,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x150d0,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_csi2phytimer_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&cam_cc_csi2phytimer_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_csi3phytimer_clk = {
|
|
.halt_reg = 0x150f0,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x150f0,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_csi3phytimer_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&cam_cc_csi3phytimer_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_csid_clk = {
|
|
.halt_reg = 0x13168,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x13168,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_csid_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&cam_cc_csid_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_csid_csiphy_rx_clk = {
|
|
.halt_reg = 0x15094,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x15094,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_csid_csiphy_rx_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&cam_cc_cphy_rx_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_csiphy0_clk = {
|
|
.halt_reg = 0x15090,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x15090,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_csiphy0_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&cam_cc_cphy_rx_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_csiphy1_clk = {
|
|
.halt_reg = 0x150b4,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x150b4,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_csiphy1_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&cam_cc_cphy_rx_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_csiphy2_clk = {
|
|
.halt_reg = 0x150d4,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x150d4,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_csiphy2_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&cam_cc_cphy_rx_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_csiphy3_clk = {
|
|
.halt_reg = 0x150f4,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x150f4,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_csiphy3_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&cam_cc_cphy_rx_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_icp_ahb_clk = {
|
|
.halt_reg = 0x1309c,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x1309c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_icp_ahb_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&cam_cc_slow_ahb_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_icp_clk = {
|
|
.halt_reg = 0x13094,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x13094,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_icp_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&cam_cc_icp_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_ife_0_clk = {
|
|
.halt_reg = 0x1101c,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x1101c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_ife_0_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&cam_cc_ife_0_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_ife_0_fast_ahb_clk = {
|
|
.halt_reg = 0x11030,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x11030,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_ife_0_fast_ahb_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&cam_cc_fast_ahb_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_ife_1_clk = {
|
|
.halt_reg = 0x1201c,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x1201c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_ife_1_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&cam_cc_ife_1_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_ife_1_fast_ahb_clk = {
|
|
.halt_reg = 0x12030,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x12030,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_ife_1_fast_ahb_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&cam_cc_fast_ahb_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_ife_lite_ahb_clk = {
|
|
.halt_reg = 0x13044,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x13044,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_ife_lite_ahb_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&cam_cc_slow_ahb_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_ife_lite_clk = {
|
|
.halt_reg = 0x13018,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x13018,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_ife_lite_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&cam_cc_ife_lite_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_ife_lite_cphy_rx_clk = {
|
|
.halt_reg = 0x13040,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x13040,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_ife_lite_cphy_rx_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&cam_cc_cphy_rx_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_ife_lite_csid_clk = {
|
|
.halt_reg = 0x13038,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x13038,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_ife_lite_csid_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&cam_cc_ife_lite_csid_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_ipe_ahb_clk = {
|
|
.halt_reg = 0x10030,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x10030,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_ipe_ahb_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&cam_cc_slow_ahb_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_ipe_clk = {
|
|
.halt_reg = 0x1001c,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x1001c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_ipe_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&cam_cc_ipe_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_ipe_fast_ahb_clk = {
|
|
.halt_reg = 0x10034,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x10034,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_ipe_fast_ahb_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&cam_cc_fast_ahb_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_mclk0_clk = {
|
|
.halt_reg = 0x1501c,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x1501c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_mclk0_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&cam_cc_mclk0_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_mclk1_clk = {
|
|
.halt_reg = 0x15038,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x15038,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_mclk1_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&cam_cc_mclk1_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_mclk2_clk = {
|
|
.halt_reg = 0x15054,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x15054,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_mclk2_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&cam_cc_mclk2_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_mclk3_clk = {
|
|
.halt_reg = 0x15070,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x15070,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_mclk3_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&cam_cc_mclk3_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_sfe_lite_0_clk = {
|
|
.halt_reg = 0x1304c,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x1304c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_sfe_lite_0_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&cam_cc_ife_0_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_sfe_lite_0_fast_ahb_clk = {
|
|
.halt_reg = 0x1305c,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x1305c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_sfe_lite_0_fast_ahb_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&cam_cc_fast_ahb_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_sfe_lite_1_clk = {
|
|
.halt_reg = 0x13064,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x13064,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_sfe_lite_1_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&cam_cc_ife_1_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_sfe_lite_1_fast_ahb_clk = {
|
|
.halt_reg = 0x13074,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x13074,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_sfe_lite_1_fast_ahb_clk",
|
|
.parent_hws = (const struct clk_hw*[]) {
|
|
&cam_cc_fast_ahb_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch cam_cc_sm_obs_clk = {
|
|
.halt_reg = 0x1510c,
|
|
.halt_check = BRANCH_HALT_SKIP,
|
|
.clkr = {
|
|
.enable_reg = 0x1510c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data) {
|
|
.name = "cam_cc_sm_obs_clk",
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct gdsc cam_cc_titan_top_gdsc = {
|
|
.gdscr = 0x131bc,
|
|
.en_rest_wait_val = 0x2,
|
|
.en_few_wait_val = 0x2,
|
|
.clk_dis_wait_val = 0xf,
|
|
.pd = {
|
|
.name = "cam_cc_titan_top_gdsc",
|
|
},
|
|
.pwrsts = PWRSTS_OFF_ON,
|
|
.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
|
|
};
|
|
|
|
static struct clk_regmap *cam_cc_sa8775p_clocks[] = {
|
|
[CAM_CC_CAMNOC_AXI_CLK] = &cam_cc_camnoc_axi_clk.clkr,
|
|
[CAM_CC_CAMNOC_AXI_CLK_SRC] = &cam_cc_camnoc_axi_clk_src.clkr,
|
|
[CAM_CC_CAMNOC_DCD_XO_CLK] = &cam_cc_camnoc_dcd_xo_clk.clkr,
|
|
[CAM_CC_CCI_0_CLK] = &cam_cc_cci_0_clk.clkr,
|
|
[CAM_CC_CCI_0_CLK_SRC] = &cam_cc_cci_0_clk_src.clkr,
|
|
[CAM_CC_CCI_1_CLK] = &cam_cc_cci_1_clk.clkr,
|
|
[CAM_CC_CCI_1_CLK_SRC] = &cam_cc_cci_1_clk_src.clkr,
|
|
[CAM_CC_CCI_2_CLK] = &cam_cc_cci_2_clk.clkr,
|
|
[CAM_CC_CCI_2_CLK_SRC] = &cam_cc_cci_2_clk_src.clkr,
|
|
[CAM_CC_CCI_3_CLK] = &cam_cc_cci_3_clk.clkr,
|
|
[CAM_CC_CCI_3_CLK_SRC] = &cam_cc_cci_3_clk_src.clkr,
|
|
[CAM_CC_CORE_AHB_CLK] = &cam_cc_core_ahb_clk.clkr,
|
|
[CAM_CC_CPAS_AHB_CLK] = &cam_cc_cpas_ahb_clk.clkr,
|
|
[CAM_CC_CPAS_FAST_AHB_CLK] = &cam_cc_cpas_fast_ahb_clk.clkr,
|
|
[CAM_CC_CPAS_IFE_0_CLK] = &cam_cc_cpas_ife_0_clk.clkr,
|
|
[CAM_CC_CPAS_IFE_1_CLK] = &cam_cc_cpas_ife_1_clk.clkr,
|
|
[CAM_CC_CPAS_IFE_LITE_CLK] = &cam_cc_cpas_ife_lite_clk.clkr,
|
|
[CAM_CC_CPAS_IPE_CLK] = &cam_cc_cpas_ipe_clk.clkr,
|
|
[CAM_CC_CPAS_SFE_LITE_0_CLK] = &cam_cc_cpas_sfe_lite_0_clk.clkr,
|
|
[CAM_CC_CPAS_SFE_LITE_1_CLK] = &cam_cc_cpas_sfe_lite_1_clk.clkr,
|
|
[CAM_CC_CPHY_RX_CLK_SRC] = &cam_cc_cphy_rx_clk_src.clkr,
|
|
[CAM_CC_CSI0PHYTIMER_CLK] = &cam_cc_csi0phytimer_clk.clkr,
|
|
[CAM_CC_CSI0PHYTIMER_CLK_SRC] = &cam_cc_csi0phytimer_clk_src.clkr,
|
|
[CAM_CC_CSI1PHYTIMER_CLK] = &cam_cc_csi1phytimer_clk.clkr,
|
|
[CAM_CC_CSI1PHYTIMER_CLK_SRC] = &cam_cc_csi1phytimer_clk_src.clkr,
|
|
[CAM_CC_CSI2PHYTIMER_CLK] = &cam_cc_csi2phytimer_clk.clkr,
|
|
[CAM_CC_CSI2PHYTIMER_CLK_SRC] = &cam_cc_csi2phytimer_clk_src.clkr,
|
|
[CAM_CC_CSI3PHYTIMER_CLK] = &cam_cc_csi3phytimer_clk.clkr,
|
|
[CAM_CC_CSI3PHYTIMER_CLK_SRC] = &cam_cc_csi3phytimer_clk_src.clkr,
|
|
[CAM_CC_CSID_CLK] = &cam_cc_csid_clk.clkr,
|
|
[CAM_CC_CSID_CLK_SRC] = &cam_cc_csid_clk_src.clkr,
|
|
[CAM_CC_CSID_CSIPHY_RX_CLK] = &cam_cc_csid_csiphy_rx_clk.clkr,
|
|
[CAM_CC_CSIPHY0_CLK] = &cam_cc_csiphy0_clk.clkr,
|
|
[CAM_CC_CSIPHY1_CLK] = &cam_cc_csiphy1_clk.clkr,
|
|
[CAM_CC_CSIPHY2_CLK] = &cam_cc_csiphy2_clk.clkr,
|
|
[CAM_CC_CSIPHY3_CLK] = &cam_cc_csiphy3_clk.clkr,
|
|
[CAM_CC_FAST_AHB_CLK_SRC] = &cam_cc_fast_ahb_clk_src.clkr,
|
|
[CAM_CC_ICP_AHB_CLK] = &cam_cc_icp_ahb_clk.clkr,
|
|
[CAM_CC_ICP_CLK] = &cam_cc_icp_clk.clkr,
|
|
[CAM_CC_ICP_CLK_SRC] = &cam_cc_icp_clk_src.clkr,
|
|
[CAM_CC_IFE_0_CLK] = &cam_cc_ife_0_clk.clkr,
|
|
[CAM_CC_IFE_0_CLK_SRC] = &cam_cc_ife_0_clk_src.clkr,
|
|
[CAM_CC_IFE_0_FAST_AHB_CLK] = &cam_cc_ife_0_fast_ahb_clk.clkr,
|
|
[CAM_CC_IFE_1_CLK] = &cam_cc_ife_1_clk.clkr,
|
|
[CAM_CC_IFE_1_CLK_SRC] = &cam_cc_ife_1_clk_src.clkr,
|
|
[CAM_CC_IFE_1_FAST_AHB_CLK] = &cam_cc_ife_1_fast_ahb_clk.clkr,
|
|
[CAM_CC_IFE_LITE_AHB_CLK] = &cam_cc_ife_lite_ahb_clk.clkr,
|
|
[CAM_CC_IFE_LITE_CLK] = &cam_cc_ife_lite_clk.clkr,
|
|
[CAM_CC_IFE_LITE_CLK_SRC] = &cam_cc_ife_lite_clk_src.clkr,
|
|
[CAM_CC_IFE_LITE_CPHY_RX_CLK] = &cam_cc_ife_lite_cphy_rx_clk.clkr,
|
|
[CAM_CC_IFE_LITE_CSID_CLK] = &cam_cc_ife_lite_csid_clk.clkr,
|
|
[CAM_CC_IFE_LITE_CSID_CLK_SRC] = &cam_cc_ife_lite_csid_clk_src.clkr,
|
|
[CAM_CC_IPE_AHB_CLK] = &cam_cc_ipe_ahb_clk.clkr,
|
|
[CAM_CC_IPE_CLK] = &cam_cc_ipe_clk.clkr,
|
|
[CAM_CC_IPE_CLK_SRC] = &cam_cc_ipe_clk_src.clkr,
|
|
[CAM_CC_IPE_FAST_AHB_CLK] = &cam_cc_ipe_fast_ahb_clk.clkr,
|
|
[CAM_CC_MCLK0_CLK] = &cam_cc_mclk0_clk.clkr,
|
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[CAM_CC_MCLK0_CLK_SRC] = &cam_cc_mclk0_clk_src.clkr,
|
|
[CAM_CC_MCLK1_CLK] = &cam_cc_mclk1_clk.clkr,
|
|
[CAM_CC_MCLK1_CLK_SRC] = &cam_cc_mclk1_clk_src.clkr,
|
|
[CAM_CC_MCLK2_CLK] = &cam_cc_mclk2_clk.clkr,
|
|
[CAM_CC_MCLK2_CLK_SRC] = &cam_cc_mclk2_clk_src.clkr,
|
|
[CAM_CC_MCLK3_CLK] = &cam_cc_mclk3_clk.clkr,
|
|
[CAM_CC_MCLK3_CLK_SRC] = &cam_cc_mclk3_clk_src.clkr,
|
|
[CAM_CC_PLL0] = &cam_cc_pll0.clkr,
|
|
[CAM_CC_PLL0_OUT_EVEN] = &cam_cc_pll0_out_even.clkr,
|
|
[CAM_CC_PLL0_OUT_ODD] = &cam_cc_pll0_out_odd.clkr,
|
|
[CAM_CC_PLL2] = &cam_cc_pll2.clkr,
|
|
[CAM_CC_PLL3] = &cam_cc_pll3.clkr,
|
|
[CAM_CC_PLL3_OUT_EVEN] = &cam_cc_pll3_out_even.clkr,
|
|
[CAM_CC_PLL4] = &cam_cc_pll4.clkr,
|
|
[CAM_CC_PLL4_OUT_EVEN] = &cam_cc_pll4_out_even.clkr,
|
|
[CAM_CC_PLL5] = &cam_cc_pll5.clkr,
|
|
[CAM_CC_PLL5_OUT_EVEN] = &cam_cc_pll5_out_even.clkr,
|
|
[CAM_CC_SFE_LITE_0_CLK] = &cam_cc_sfe_lite_0_clk.clkr,
|
|
[CAM_CC_SFE_LITE_0_FAST_AHB_CLK] = &cam_cc_sfe_lite_0_fast_ahb_clk.clkr,
|
|
[CAM_CC_SFE_LITE_1_CLK] = &cam_cc_sfe_lite_1_clk.clkr,
|
|
[CAM_CC_SFE_LITE_1_FAST_AHB_CLK] = &cam_cc_sfe_lite_1_fast_ahb_clk.clkr,
|
|
[CAM_CC_SLEEP_CLK_SRC] = &cam_cc_sleep_clk_src.clkr,
|
|
[CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr,
|
|
[CAM_CC_SM_OBS_CLK] = &cam_cc_sm_obs_clk.clkr,
|
|
[CAM_CC_XO_CLK_SRC] = &cam_cc_xo_clk_src.clkr,
|
|
[CAM_CC_QDSS_DEBUG_XO_CLK] = &cam_cc_qdss_debug_xo_clk.clkr,
|
|
};
|
|
|
|
static struct gdsc *cam_cc_sa8775p_gdscs[] = {
|
|
[CAM_CC_TITAN_TOP_GDSC] = &cam_cc_titan_top_gdsc,
|
|
};
|
|
|
|
static const struct qcom_reset_map cam_cc_sa8775p_resets[] = {
|
|
[CAM_CC_ICP_BCR] = { 0x13078 },
|
|
[CAM_CC_IFE_0_BCR] = { 0x11000 },
|
|
[CAM_CC_IFE_1_BCR] = { 0x12000 },
|
|
[CAM_CC_IPE_0_BCR] = { 0x10000 },
|
|
[CAM_CC_SFE_LITE_0_BCR] = { 0x13048 },
|
|
[CAM_CC_SFE_LITE_1_BCR] = { 0x13060 },
|
|
};
|
|
|
|
static const struct regmap_config cam_cc_sa8775p_regmap_config = {
|
|
.reg_bits = 32,
|
|
.reg_stride = 4,
|
|
.val_bits = 32,
|
|
.max_register = 0x16218,
|
|
.fast_io = true,
|
|
};
|
|
|
|
static struct qcom_cc_desc cam_cc_sa8775p_desc = {
|
|
.config = &cam_cc_sa8775p_regmap_config,
|
|
.clks = cam_cc_sa8775p_clocks,
|
|
.num_clks = ARRAY_SIZE(cam_cc_sa8775p_clocks),
|
|
.resets = cam_cc_sa8775p_resets,
|
|
.num_resets = ARRAY_SIZE(cam_cc_sa8775p_resets),
|
|
.gdscs = cam_cc_sa8775p_gdscs,
|
|
.num_gdscs = ARRAY_SIZE(cam_cc_sa8775p_gdscs),
|
|
};
|
|
|
|
static const struct of_device_id cam_cc_sa8775p_match_table[] = {
|
|
{ .compatible = "qcom,sa8775p-camcc" },
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, cam_cc_sa8775p_match_table);
|
|
|
|
static int cam_cc_sa8775p_probe(struct platform_device *pdev)
|
|
{
|
|
struct regmap *regmap;
|
|
int ret;
|
|
|
|
ret = devm_pm_runtime_enable(&pdev->dev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = pm_runtime_resume_and_get(&pdev->dev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
regmap = qcom_cc_map(pdev, &cam_cc_sa8775p_desc);
|
|
if (IS_ERR(regmap)) {
|
|
pm_runtime_put(&pdev->dev);
|
|
return PTR_ERR(regmap);
|
|
}
|
|
|
|
clk_lucid_evo_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config);
|
|
clk_rivian_evo_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config);
|
|
clk_lucid_evo_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config);
|
|
clk_lucid_evo_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config);
|
|
clk_lucid_evo_pll_configure(&cam_cc_pll5, regmap, &cam_cc_pll5_config);
|
|
|
|
/* Keep some clocks always enabled */
|
|
qcom_branch_set_clk_en(regmap, 0x13194); /* CAM_CC_CAMNOC_XO_CLK */
|
|
qcom_branch_set_clk_en(regmap, 0x131ec); /* CAM_CC_GDSC_CLK */
|
|
qcom_branch_set_clk_en(regmap, 0x13208); /* CAM_CC_SLEEP_CLK */
|
|
|
|
ret = qcom_cc_really_probe(&pdev->dev, &cam_cc_sa8775p_desc, regmap);
|
|
|
|
pm_runtime_put(&pdev->dev);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static struct platform_driver cam_cc_sa8775p_driver = {
|
|
.probe = cam_cc_sa8775p_probe,
|
|
.driver = {
|
|
.name = "camcc-sa8775p",
|
|
.of_match_table = cam_cc_sa8775p_match_table,
|
|
},
|
|
};
|
|
|
|
module_platform_driver(cam_cc_sa8775p_driver);
|
|
|
|
MODULE_DESCRIPTION("QTI CAMCC SA8775P Driver");
|
|
MODULE_LICENSE("GPL");
|