54 lines
1.6 KiB
C
54 lines
1.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2022 Yassine Oudjana <y.oudjana@protonmail.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/platform_device.h>
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#include "clk-gate.h"
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#include "clk-mtk.h"
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#include <dt-bindings/clock/mediatek,mt6735-vencsys.h>
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#define VENC_CG_CON 0x00
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#define VENC_CG_SET 0x04
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#define VENC_CG_CLR 0x08
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static struct mtk_gate_regs venc_cg_regs = {
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.set_ofs = VENC_CG_SET,
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.clr_ofs = VENC_CG_CLR,
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.sta_ofs = VENC_CG_CON,
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};
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static const struct mtk_gate vencsys_gates[] = {
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GATE_MTK(CLK_VENC_SMI_LARB3, "smi_larb3", "mm_sel", &venc_cg_regs, 0, &mtk_clk_gate_ops_setclr_inv),
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GATE_MTK(CLK_VENC_VENC, "venc", "mm_sel", &venc_cg_regs, 4, &mtk_clk_gate_ops_setclr_inv),
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GATE_MTK(CLK_VENC_JPGENC, "jpgenc", "mm_sel", &venc_cg_regs, 8, &mtk_clk_gate_ops_setclr_inv),
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GATE_MTK(CLK_VENC_JPGDEC, "jpgdec", "mm_sel", &venc_cg_regs, 12, &mtk_clk_gate_ops_setclr_inv),
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};
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static const struct mtk_clk_desc vencsys_clks = {
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.clks = vencsys_gates,
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.num_clks = ARRAY_SIZE(vencsys_gates),
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};
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static const struct of_device_id of_match_mt6735_vencsys[] = {
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{ .compatible = "mediatek,mt6735-vencsys", .data = &vencsys_clks },
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{ /* sentinel */ }
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};
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static struct platform_driver clk_mt6735_vencsys = {
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.probe = mtk_clk_simple_probe,
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.remove = mtk_clk_simple_remove,
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.driver = {
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.name = "clk-mt6735-vencsys",
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.of_match_table = of_match_mt6735_vencsys,
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},
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};
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module_platform_driver(clk_mt6735_vencsys);
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MODULE_AUTHOR("Yassine Oudjana <y.oudjana@protonmail.com>");
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MODULE_DESCRIPTION("Mediatek MT6735 vencsys clock driver");
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MODULE_LICENSE("GPL");
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