164 lines
3.9 KiB
Plaintext
164 lines
3.9 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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/*
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* Copyright 2024 Mobileye Vision Technologies Ltd.
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*/
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#include <dt-bindings/interrupt-controller/mips-gic.h>
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#include <dt-bindings/clock/mobileye,eyeq5-clk.h>
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "img,i6500";
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reg = <0>;
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clocks = <&olb_central EQ6HC_CENTRAL_CPU_OCC>;
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};
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};
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aliases {
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serial0 = &uart0;
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};
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cpu_intc: interrupt-controller {
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compatible = "mti,cpu-interrupt-controller";
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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};
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xtal: clock-30000000 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <30000000>;
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};
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soc: soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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olb_acc: system-controller@d2003000 {
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compatible = "mobileye,eyeq6h-acc-olb", "syscon";
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reg = <0x0 0xd2003000 0x0 0x1000>;
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#reset-cells = <1>;
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#clock-cells = <1>;
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clocks = <&xtal>;
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clock-names = "ref";
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};
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olb_central: system-controller@d3100000 {
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compatible = "mobileye,eyeq6h-central-olb", "syscon";
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reg = <0x0 0xd3100000 0x0 0x1000>;
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#clock-cells = <1>;
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clocks = <&xtal>;
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clock-names = "ref";
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};
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uart0: serial@d3331000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0 0xd3331000 0x0 0x1000>;
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reg-io-width = <4>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SHARED 43 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&olb_west EQ6HC_WEST_PER_UART>, <&olb_west EQ6HC_WEST_PER_OCC>;
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clock-names = "uartclk", "apb_pclk";
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};
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pinctrl_west: pinctrl@d3337000 {
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compatible = "pinctrl-single";
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reg = <0x0 0xd3337000 0x0 0xb0>;
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#pinctrl-cells = <1>;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0xffff>;
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};
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olb_west: system-controller@d3338000 {
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compatible = "mobileye,eyeq6h-west-olb", "syscon";
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reg = <0x0 0xd3338000 0x0 0x1000>;
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#reset-cells = <1>;
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#clock-cells = <1>;
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clocks = <&xtal>;
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clock-names = "ref";
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};
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pinctrl_east: pinctrl@d3357000 {
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compatible = "pinctrl-single";
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reg = <0x0 0xd3357000 0x0 0xb0>;
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#pinctrl-cells = <1>;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0xffff>;
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};
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olb_east: system-controller@d3358000 {
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compatible = "mobileye,eyeq6h-east-olb", "syscon";
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reg = <0x0 0xd3358000 0x0 0x1000>;
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#reset-cells = <1>;
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#clock-cells = <1>;
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clocks = <&xtal>;
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clock-names = "ref";
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};
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olb_south: system-controller@d8013000 {
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compatible = "mobileye,eyeq6h-south-olb", "syscon";
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reg = <0x0 0xd8013000 0x0 0x1000>;
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#clock-cells = <1>;
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clocks = <&xtal>;
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clock-names = "ref";
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};
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pinctrl_south: pinctrl@d8014000 {
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compatible = "pinctrl-single";
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reg = <0x0 0xd8014000 0x0 0xf8>;
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#pinctrl-cells = <1>;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0xffff>;
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};
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olb_ddr0: system-controller@e4080000 {
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compatible = "mobileye,eyeq6h-ddr0-olb", "syscon";
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reg = <0x0 0xe4080000 0x0 0x1000>;
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#clock-cells = <1>;
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clocks = <&xtal>;
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clock-names = "ref";
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};
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olb_ddr1: system-controller@e4081000 {
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compatible = "mobileye,eyeq6h-ddr1-olb", "syscon";
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reg = <0x0 0xe4081000 0x0 0x1000>;
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#clock-cells = <1>;
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clocks = <&xtal>;
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clock-names = "ref";
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};
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gic: interrupt-controller@f0920000 {
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compatible = "mti,gic";
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reg = <0x0 0xf0920000 0x0 0x20000>;
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interrupt-controller;
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#interrupt-cells = <3>;
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/*
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* Declare the interrupt-parent even though the mti,gic
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* binding doesn't require it, such that the kernel can
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* figure out that cpu_intc is the root interrupt
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* controller & should be probed first.
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*/
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interrupt-parent = <&cpu_intc>;
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timer {
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compatible = "mti,gic-timer";
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interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
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clocks = <&olb_central EQ6HC_CENTRAL_CPU_OCC>;
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};
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};
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};
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};
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#include "eyeq6h-pins.dtsi"
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