363 lines
14 KiB
Plaintext
363 lines
14 KiB
Plaintext
Using TopDown metrics
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---------------------
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TopDown metrics break apart performance bottlenecks. Starting at level
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1 it is typical to get metrics on retiring, bad speculation, frontend
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bound, and backend bound. Higher levels provide more detail in to the
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level 1 bottlenecks, such as at level 2: core bound, memory bound,
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heavy operations, light operations, branch mispredicts, machine
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clears, fetch latency and fetch bandwidth. For more details see [1][2][3].
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perf stat --topdown implements this using available metrics that vary
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per architecture.
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% perf stat -a --topdown -I1000
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# time % tma_retiring % tma_backend_bound % tma_frontend_bound % tma_bad_speculation
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1.001141351 11.5 34.9 46.9 6.7
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2.006141972 13.4 28.1 50.4 8.1
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3.010162040 12.9 28.1 51.1 8.0
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4.014009311 12.5 28.6 51.8 7.2
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5.017838554 11.8 33.0 48.0 7.2
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5.704818971 14.0 27.5 51.3 7.3
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...
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New Topdown features in Intel Ice Lake
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======================================
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With Ice Lake CPUs the TopDown metrics are directly available as
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fixed counters and do not require generic counters. This allows
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to collect TopDown always in addition to other events.
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Using TopDown through RDPMC in applications on Intel Ice Lake
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=============================================================
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For more fine grained measurements it can be useful to
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access the new directly from user space. This is more complicated,
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but drastically lowers overhead.
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On Ice Lake, there is a new fixed counter 3: SLOTS, which reports
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"pipeline SLOTS" (cycles multiplied by core issue width) and a
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metric register that reports slots ratios for the different bottleneck
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categories.
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The metrics counter is CPU model specific and is not available on older
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CPUs.
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Example code
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============
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Library functions to do the functionality described below
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is also available in libjevents [4]
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The application opens a group with fixed counter 3 (SLOTS) and any
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metric event, and allow user programs to read the performance counters.
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Fixed counter 3 is mapped to a pseudo event event=0x00, umask=04,
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so the perf_event_attr structure should be initialized with
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{ .config = 0x0400, .type = PERF_TYPE_RAW }
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The metric events are mapped to the pseudo event event=0x00, umask=0x8X.
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For example, the perf_event_attr structure can be initialized with
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{ .config = 0x8000, .type = PERF_TYPE_RAW } for Retiring metric event
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The Fixed counter 3 must be the leader of the group.
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#include <linux/perf_event.h>
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#include <sys/mman.h>
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#include <sys/syscall.h>
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#include <unistd.h>
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/* Provide own perf_event_open stub because glibc doesn't */
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__attribute__((weak))
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int perf_event_open(struct perf_event_attr *attr, pid_t pid,
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int cpu, int group_fd, unsigned long flags)
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{
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return syscall(__NR_perf_event_open, attr, pid, cpu, group_fd, flags);
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}
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/* Open slots counter file descriptor for current task. */
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struct perf_event_attr slots = {
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.type = PERF_TYPE_RAW,
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.size = sizeof(struct perf_event_attr),
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.config = 0x400,
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.exclude_kernel = 1,
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};
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int slots_fd = perf_event_open(&slots, 0, -1, -1, 0);
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if (slots_fd < 0)
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... error ...
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/* Memory mapping the fd permits _rdpmc calls from userspace */
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void *slots_p = mmap(0, getpagesize(), PROT_READ, MAP_SHARED, slots_fd, 0);
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if (!slot_p)
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.... error ...
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/*
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* Open metrics event file descriptor for current task.
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* Set slots event as the leader of the group.
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*/
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struct perf_event_attr metrics = {
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.type = PERF_TYPE_RAW,
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.size = sizeof(struct perf_event_attr),
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.config = 0x8000,
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.exclude_kernel = 1,
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};
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int metrics_fd = perf_event_open(&metrics, 0, -1, slots_fd, 0);
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if (metrics_fd < 0)
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... error ...
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/* Memory mapping the fd permits _rdpmc calls from userspace */
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void *metrics_p = mmap(0, getpagesize(), PROT_READ, MAP_SHARED, metrics_fd, 0);
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if (!metrics_p)
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... error ...
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Note: the file descriptors returned by the perf_event_open calls must be memory
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mapped to permit calls to the _rdpmd instruction. Permission may also be granted
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by writing the /sys/devices/cpu/rdpmc sysfs node.
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The RDPMC instruction (or _rdpmc compiler intrinsic) can now be used
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to read slots and the topdown metrics at different points of the program:
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#include <stdint.h>
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#include <x86intrin.h>
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#define RDPMC_FIXED (1 << 30) /* return fixed counters */
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#define RDPMC_METRIC (1 << 29) /* return metric counters */
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#define FIXED_COUNTER_SLOTS 3
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#define METRIC_COUNTER_TOPDOWN_L1_L2 0
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static inline uint64_t read_slots(void)
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{
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return _rdpmc(RDPMC_FIXED | FIXED_COUNTER_SLOTS);
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}
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static inline uint64_t read_metrics(void)
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{
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return _rdpmc(RDPMC_METRIC | METRIC_COUNTER_TOPDOWN_L1_L2);
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}
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Then the program can be instrumented to read these metrics at different
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points.
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It's not a good idea to do this with too short code regions,
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as the parallelism and overlap in the CPU program execution will
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cause too much measurement inaccuracy. For example instrumenting
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individual basic blocks is definitely too fine grained.
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_rdpmc calls should not be mixed with reading the metrics and slots counters
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through system calls, as the kernel will reset these counters after each system
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call.
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Decoding metrics values
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=======================
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The value reported by read_metrics() contains four 8 bit fields
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that represent a scaled ratio that represent the Level 1 bottleneck.
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All four fields add up to 0xff (= 100%)
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The binary ratios in the metric value can be converted to float ratios:
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#define GET_METRIC(m, i) (((m) >> (i*8)) & 0xff)
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/* L1 Topdown metric events */
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#define TOPDOWN_RETIRING(val) ((float)GET_METRIC(val, 0) / 0xff)
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#define TOPDOWN_BAD_SPEC(val) ((float)GET_METRIC(val, 1) / 0xff)
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#define TOPDOWN_FE_BOUND(val) ((float)GET_METRIC(val, 2) / 0xff)
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#define TOPDOWN_BE_BOUND(val) ((float)GET_METRIC(val, 3) / 0xff)
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/*
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* L2 Topdown metric events.
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* Available on Sapphire Rapids and later platforms.
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*/
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#define TOPDOWN_HEAVY_OPS(val) ((float)GET_METRIC(val, 4) / 0xff)
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#define TOPDOWN_BR_MISPREDICT(val) ((float)GET_METRIC(val, 5) / 0xff)
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#define TOPDOWN_FETCH_LAT(val) ((float)GET_METRIC(val, 6) / 0xff)
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#define TOPDOWN_MEM_BOUND(val) ((float)GET_METRIC(val, 7) / 0xff)
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and then converted to percent for printing.
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The ratios in the metric accumulate for the time when the counter
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is enabled. For measuring programs it is often useful to measure
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specific sections. For this it is needed to deltas on metrics.
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This can be done by scaling the metrics with the slots counter
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read at the same time.
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Then it's possible to take deltas of these slots counts
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measured at different points, and determine the metrics
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for that time period.
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slots_a = read_slots();
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metric_a = read_metrics();
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... larger code region ...
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slots_b = read_slots()
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metric_b = read_metrics()
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# compute scaled metrics for measurement a
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retiring_slots_a = GET_METRIC(metric_a, 0) * slots_a
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bad_spec_slots_a = GET_METRIC(metric_a, 1) * slots_a
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fe_bound_slots_a = GET_METRIC(metric_a, 2) * slots_a
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be_bound_slots_a = GET_METRIC(metric_a, 3) * slots_a
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# compute delta scaled metrics between b and a
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retiring_slots = GET_METRIC(metric_b, 0) * slots_b - retiring_slots_a
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bad_spec_slots = GET_METRIC(metric_b, 1) * slots_b - bad_spec_slots_a
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fe_bound_slots = GET_METRIC(metric_b, 2) * slots_b - fe_bound_slots_a
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be_bound_slots = GET_METRIC(metric_b, 3) * slots_b - be_bound_slots_a
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Later the individual ratios of L1 metric events for the measurement period can
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be recreated from these counts.
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slots_delta = slots_b - slots_a
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retiring_ratio = (float)retiring_slots / slots_delta
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bad_spec_ratio = (float)bad_spec_slots / slots_delta
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fe_bound_ratio = (float)fe_bound_slots / slots_delta
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be_bound_ratio = (float)be_bound_slots / slota_delta
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printf("Retiring %.2f%% Bad Speculation %.2f%% FE Bound %.2f%% BE Bound %.2f%%\n",
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retiring_ratio * 100.,
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bad_spec_ratio * 100.,
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fe_bound_ratio * 100.,
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be_bound_ratio * 100.);
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The individual ratios of L2 metric events for the measurement period can be
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recreated from L1 and L2 metric counters. (Available on Sapphire Rapids and
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later platforms)
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# compute scaled metrics for measurement a
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heavy_ops_slots_a = GET_METRIC(metric_a, 4) * slots_a
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br_mispredict_slots_a = GET_METRIC(metric_a, 5) * slots_a
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fetch_lat_slots_a = GET_METRIC(metric_a, 6) * slots_a
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mem_bound_slots_a = GET_METRIC(metric_a, 7) * slots_a
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# compute delta scaled metrics between b and a
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heavy_ops_slots = GET_METRIC(metric_b, 4) * slots_b - heavy_ops_slots_a
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br_mispredict_slots = GET_METRIC(metric_b, 5) * slots_b - br_mispredict_slots_a
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fetch_lat_slots = GET_METRIC(metric_b, 6) * slots_b - fetch_lat_slots_a
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mem_bound_slots = GET_METRIC(metric_b, 7) * slots_b - mem_bound_slots_a
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slots_delta = slots_b - slots_a
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heavy_ops_ratio = (float)heavy_ops_slots / slots_delta
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light_ops_ratio = retiring_ratio - heavy_ops_ratio;
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br_mispredict_ratio = (float)br_mispredict_slots / slots_delta
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machine_clears_ratio = bad_spec_ratio - br_mispredict_ratio;
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fetch_lat_ratio = (float)fetch_lat_slots / slots_delta
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fetch_bw_ratio = fe_bound_ratio - fetch_lat_ratio;
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mem_bound_ratio = (float)mem_bound_slots / slota_delta
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core_bound_ratio = be_bound_ratio - mem_bound_ratio;
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printf("Heavy Operations %.2f%% Light Operations %.2f%% "
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"Branch Mispredict %.2f%% Machine Clears %.2f%% "
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"Fetch Latency %.2f%% Fetch Bandwidth %.2f%% "
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"Mem Bound %.2f%% Core Bound %.2f%%\n",
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heavy_ops_ratio * 100.,
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light_ops_ratio * 100.,
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br_mispredict_ratio * 100.,
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machine_clears_ratio * 100.,
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fetch_lat_ratio * 100.,
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fetch_bw_ratio * 100.,
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mem_bound_ratio * 100.,
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core_bound_ratio * 100.);
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Resetting metrics counters
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==========================
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Since the individual metrics are only 8bit they lose precision for
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short regions over time because the number of cycles covered by each
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fraction bit shrinks. So the counters need to be reset regularly.
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When using the kernel perf API the kernel resets on every read.
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So as long as the reading is at reasonable intervals (every few
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seconds) the precision is good.
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When using perf stat it is recommended to always use the -I option,
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with no longer interval than a few seconds
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perf stat -I 1000 --topdown ...
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For user programs using RDPMC directly the counter can
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be reset explicitly using ioctl:
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ioctl(perf_fd, PERF_EVENT_IOC_RESET, 0);
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This "opens" a new measurement period.
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A program using RDPMC for TopDown should schedule such a reset
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regularly, as in every few seconds.
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Limits on Intel Ice Lake
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========================
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Four pseudo TopDown metric events are exposed for the end-users,
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topdown-retiring, topdown-bad-spec, topdown-fe-bound and topdown-be-bound.
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They can be used to collect the TopDown value under the following
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rules:
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- All the TopDown metric events must be in a group with the SLOTS event.
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- The SLOTS event must be the leader of the group.
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- The PERF_FORMAT_GROUP flag must be applied for each TopDown metric
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events
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The SLOTS event and the TopDown metric events can be counting members of
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a sampling read group. Since the SLOTS event must be the leader of a TopDown
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group, the second event of the group is the sampling event.
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For example, perf record -e '{slots, $sampling_event, topdown-retiring}:S'
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Extension on Intel Sapphire Rapids Server
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=========================================
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The metrics counter is extended to support TMA method level 2 metrics.
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The lower half of the register is the TMA level 1 metrics (legacy).
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The upper half is also divided into four 8-bit fields for the new level 2
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metrics. Four more TopDown metric events are exposed for the end-users,
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topdown-heavy-ops, topdown-br-mispredict, topdown-fetch-lat and
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topdown-mem-bound.
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Each of the new level 2 metrics in the upper half is a subset of the
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corresponding level 1 metric in the lower half. Software can deduce the
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other four level 2 metrics by subtracting corresponding metrics as below.
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Light_Operations = Retiring - Heavy_Operations
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Machine_Clears = Bad_Speculation - Branch_Mispredicts
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Fetch_Bandwidth = Frontend_Bound - Fetch_Latency
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Core_Bound = Backend_Bound - Memory_Bound
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TPEBS in TopDown
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================
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TPEBS (Timed PEBS) is one of the new Intel PMU features provided since Granite
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Rapids microarchitecture. The TPEBS feature adds a 16 bit retire_latency field
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in the Basic Info group of the PEBS record. It records the Core cycles since the
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retirement of the previous instruction to the retirement of current instruction.
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Please refer to Section 8.4.1 of "Intel® Architecture Instruction Set Extensions
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Programming Reference" for more details about this feature. Because this feature
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extends PEBS record, sampling with weight option is required to get the
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retire_latency value.
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perf record -e event_name -W ...
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In the most recent release of TMA, the metrics begin to use event retire_latency
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values in some of the metrics’ formulas on processors that support TPEBS feature.
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For previous generations that do not support TPEBS, the values are static and
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predefined per processor family by the hardware architects. Due to the diversity
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of workloads in execution environments, retire_latency values measured at real
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time are more accurate. Therefore, new TMA metrics that use TPEBS will provide
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more accurate performance analysis results.
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To support TPEBS in TMA metrics, a new modifier :R on event is added. Perf would
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capture retire_latency value of required events(event with :R in metric formula)
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with perf record. The retire_latency value would be used in metric calculation.
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Currently, this feature is supported through perf stat
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perf stat -M metric_name --record-tpebs ...
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[1] https://software.intel.com/en-us/top-down-microarchitecture-analysis-method-win
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[2] https://sites.google.com/site/analysismethods/yasin-pubs
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[3] https://perf.wiki.kernel.org/index.php/Top-Down_Analysis
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[4] https://github.com/andikleen/pmu-tools/tree/master/jevents
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