102 lines
1.8 KiB
ArmAsm
102 lines
1.8 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2023 Intel Corporation
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*/
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#ifndef __ASSEMBLY__
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#define __ASSEMBLY__
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#endif
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#include <asm/csr.h>
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.macro save_context
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addi sp, sp, (-8*34)
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sd x1, 0(sp)
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sd x2, 8(sp)
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sd x3, 16(sp)
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sd x4, 24(sp)
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sd x5, 32(sp)
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sd x6, 40(sp)
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sd x7, 48(sp)
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sd x8, 56(sp)
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sd x9, 64(sp)
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sd x10, 72(sp)
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sd x11, 80(sp)
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sd x12, 88(sp)
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sd x13, 96(sp)
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sd x14, 104(sp)
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sd x15, 112(sp)
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sd x16, 120(sp)
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sd x17, 128(sp)
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sd x18, 136(sp)
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sd x19, 144(sp)
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sd x20, 152(sp)
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sd x21, 160(sp)
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sd x22, 168(sp)
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sd x23, 176(sp)
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sd x24, 184(sp)
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sd x25, 192(sp)
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sd x26, 200(sp)
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sd x27, 208(sp)
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sd x28, 216(sp)
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sd x29, 224(sp)
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sd x30, 232(sp)
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sd x31, 240(sp)
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csrr s0, CSR_SEPC
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csrr s1, CSR_SSTATUS
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csrr s2, CSR_SCAUSE
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sd s0, 248(sp)
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sd s1, 256(sp)
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sd s2, 264(sp)
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.endm
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.macro restore_context
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ld s2, 264(sp)
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ld s1, 256(sp)
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ld s0, 248(sp)
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csrw CSR_SCAUSE, s2
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csrw CSR_SSTATUS, s1
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csrw CSR_SEPC, s0
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ld x31, 240(sp)
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ld x30, 232(sp)
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ld x29, 224(sp)
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ld x28, 216(sp)
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ld x27, 208(sp)
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ld x26, 200(sp)
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ld x25, 192(sp)
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ld x24, 184(sp)
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ld x23, 176(sp)
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ld x22, 168(sp)
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ld x21, 160(sp)
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ld x20, 152(sp)
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ld x19, 144(sp)
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ld x18, 136(sp)
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ld x17, 128(sp)
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ld x16, 120(sp)
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ld x15, 112(sp)
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ld x14, 104(sp)
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ld x13, 96(sp)
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ld x12, 88(sp)
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ld x11, 80(sp)
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ld x10, 72(sp)
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ld x9, 64(sp)
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ld x8, 56(sp)
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ld x7, 48(sp)
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ld x6, 40(sp)
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ld x5, 32(sp)
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ld x4, 24(sp)
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ld x3, 16(sp)
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ld x2, 8(sp)
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ld x1, 0(sp)
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addi sp, sp, (8*34)
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.endm
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.balign 4
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.global exception_vectors
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exception_vectors:
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save_context
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move a0, sp
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call route_exception
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restore_context
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sret
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