129 lines
2.9 KiB
C
129 lines
2.9 KiB
C
/* SPDX-License-Identifier: ISC */
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/*
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* Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
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*/
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#ifndef __MT76_DMA_H
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#define __MT76_DMA_H
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#define DMA_DUMMY_DATA ((void *)~0)
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#define MT_RING_SIZE 0x10
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#define MT_DMA_CTL_SD_LEN1 GENMASK(13, 0)
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#define MT_DMA_CTL_LAST_SEC1 BIT(14)
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#define MT_DMA_CTL_BURST BIT(15)
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#define MT_DMA_CTL_SD_LEN0 GENMASK(29, 16)
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#define MT_DMA_CTL_LAST_SEC0 BIT(30)
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#define MT_DMA_CTL_DMA_DONE BIT(31)
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#define MT_DMA_CTL_TO_HOST BIT(8)
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#define MT_DMA_CTL_TO_HOST_A BIT(12)
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#define MT_DMA_CTL_DROP BIT(14)
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#define MT_DMA_CTL_TOKEN GENMASK(31, 16)
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#define MT_DMA_CTL_SDP1_H GENMASK(19, 16)
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#define MT_DMA_CTL_SDP0_H GENMASK(3, 0)
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#define MT_DMA_CTL_WO_DROP BIT(8)
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#define MT_DMA_PPE_CPU_REASON GENMASK(15, 11)
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#define MT_DMA_PPE_ENTRY GENMASK(30, 16)
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#define MT_DMA_INFO_DMA_FRAG BIT(9)
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#define MT_DMA_INFO_PPE_VLD BIT(31)
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#define MT_DMA_CTL_PN_CHK_FAIL BIT(13)
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#define MT_DMA_CTL_VER_MASK BIT(7)
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#define MT_DMA_RRO_EN BIT(13)
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#define MT_DMA_WED_IND_CMD_CNT 8
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#define MT_DMA_WED_IND_REASON GENMASK(15, 12)
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#define MT_DMA_HDR_LEN 4
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#define MT_RX_INFO_LEN 4
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#define MT_FCE_INFO_LEN 4
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#define MT_RX_RXWI_LEN 32
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struct mt76_desc {
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__le32 buf0;
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__le32 ctrl;
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__le32 buf1;
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__le32 info;
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} __packed __aligned(4);
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struct mt76_wed_rro_desc {
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__le32 buf0;
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__le32 buf1;
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} __packed __aligned(4);
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enum mt76_qsel {
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MT_QSEL_MGMT,
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MT_QSEL_HCCA,
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MT_QSEL_EDCA,
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MT_QSEL_EDCA_2,
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};
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enum mt76_mcu_evt_type {
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EVT_CMD_DONE,
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EVT_CMD_ERROR,
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EVT_CMD_RETRY,
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EVT_EVENT_PWR_RSP,
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EVT_EVENT_WOW_RSP,
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EVT_EVENT_CARRIER_DETECT_RSP,
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EVT_EVENT_DFS_DETECT_RSP,
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};
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enum mt76_dma_wed_ind_reason {
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MT_DMA_WED_IND_REASON_NORMAL,
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MT_DMA_WED_IND_REASON_REPEAT,
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MT_DMA_WED_IND_REASON_OLDPKT,
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};
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int mt76_dma_rx_poll(struct napi_struct *napi, int budget);
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void mt76_dma_attach(struct mt76_dev *dev);
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void mt76_dma_cleanup(struct mt76_dev *dev);
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int mt76_dma_rx_fill(struct mt76_dev *dev, struct mt76_queue *q,
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bool allow_direct);
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void __mt76_dma_queue_reset(struct mt76_dev *dev, struct mt76_queue *q,
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bool reset_idx);
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void mt76_dma_queue_reset(struct mt76_dev *dev, struct mt76_queue *q);
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static inline void
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mt76_dma_reset_tx_queue(struct mt76_dev *dev, struct mt76_queue *q)
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{
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dev->queue_ops->reset_q(dev, q);
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if (mtk_wed_device_active(&dev->mmio.wed))
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mt76_wed_dma_setup(dev, q, true);
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}
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static inline void
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mt76_dma_should_drop_buf(bool *drop, u32 ctrl, u32 buf1, u32 info)
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{
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if (!drop)
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return;
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*drop = !!(ctrl & (MT_DMA_CTL_TO_HOST_A | MT_DMA_CTL_DROP));
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if (!(ctrl & MT_DMA_CTL_VER_MASK))
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return;
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switch (FIELD_GET(MT_DMA_WED_IND_REASON, buf1)) {
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case MT_DMA_WED_IND_REASON_REPEAT:
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*drop = true;
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break;
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case MT_DMA_WED_IND_REASON_OLDPKT:
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*drop = !(info & MT_DMA_INFO_DMA_FRAG);
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break;
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default:
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*drop = !!(ctrl & MT_DMA_CTL_PN_CHK_FAIL);
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break;
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}
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}
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static inline void *mt76_priv(struct net_device *dev)
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{
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struct mt76_dev **priv;
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priv = netdev_priv(dev);
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return *priv;
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}
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#endif
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