664 lines
18 KiB
C
664 lines
18 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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#include <linux/phy.h>
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#include <linux/module.h>
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#include "qcom.h"
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/* ADC threshold */
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#define QCA808X_PHY_DEBUG_ADC_THRESHOLD 0x2c80
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#define QCA808X_ADC_THRESHOLD_MASK GENMASK(7, 0)
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#define QCA808X_ADC_THRESHOLD_80MV 0
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#define QCA808X_ADC_THRESHOLD_100MV 0xf0
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#define QCA808X_ADC_THRESHOLD_200MV 0x0f
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#define QCA808X_ADC_THRESHOLD_300MV 0xff
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/* CLD control */
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#define QCA808X_PHY_MMD3_ADDR_CLD_CTRL7 0x8007
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#define QCA808X_8023AZ_AFE_CTRL_MASK GENMASK(8, 4)
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#define QCA808X_8023AZ_AFE_EN 0x90
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/* AZ control */
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#define QCA808X_PHY_MMD3_AZ_TRAINING_CTRL 0x8008
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#define QCA808X_MMD3_AZ_TRAINING_VAL 0x1c32
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#define QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB 0x8014
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#define QCA808X_MSE_THRESHOLD_20DB_VALUE 0x529
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#define QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB 0x800E
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#define QCA808X_MSE_THRESHOLD_17DB_VALUE 0x341
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#define QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB 0x801E
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#define QCA808X_MSE_THRESHOLD_27DB_VALUE 0x419
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#define QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB 0x8020
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#define QCA808X_MSE_THRESHOLD_28DB_VALUE 0x341
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#define QCA808X_PHY_MMD7_TOP_OPTION1 0x901c
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#define QCA808X_TOP_OPTION1_DATA 0x0
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#define QCA808X_PHY_MMD3_DEBUG_1 0xa100
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#define QCA808X_MMD3_DEBUG_1_VALUE 0x9203
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#define QCA808X_PHY_MMD3_DEBUG_2 0xa101
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#define QCA808X_MMD3_DEBUG_2_VALUE 0x48ad
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#define QCA808X_PHY_MMD3_DEBUG_3 0xa103
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#define QCA808X_MMD3_DEBUG_3_VALUE 0x1698
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#define QCA808X_PHY_MMD3_DEBUG_4 0xa105
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#define QCA808X_MMD3_DEBUG_4_VALUE 0x8001
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#define QCA808X_PHY_MMD3_DEBUG_5 0xa106
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#define QCA808X_MMD3_DEBUG_5_VALUE 0x1111
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#define QCA808X_PHY_MMD3_DEBUG_6 0xa011
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#define QCA808X_MMD3_DEBUG_6_VALUE 0x5f85
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/* master/slave seed config */
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#define QCA808X_PHY_DEBUG_LOCAL_SEED 9
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#define QCA808X_MASTER_SLAVE_SEED_ENABLE BIT(1)
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#define QCA808X_MASTER_SLAVE_SEED_CFG GENMASK(12, 2)
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#define QCA808X_MASTER_SLAVE_SEED_RANGE 0x32
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/* Hibernation yields lower power consumpiton in contrast with normal operation mode.
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* when the copper cable is unplugged, the PHY enters into hibernation mode in about 10s.
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*/
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#define QCA808X_DBG_AN_TEST 0xb
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#define QCA808X_HIBERNATION_EN BIT(15)
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#define QCA808X_MMD7_LED2_CTRL 0x8074
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#define QCA808X_MMD7_LED2_FORCE_CTRL 0x8075
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#define QCA808X_MMD7_LED1_CTRL 0x8076
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#define QCA808X_MMD7_LED1_FORCE_CTRL 0x8077
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#define QCA808X_MMD7_LED0_CTRL 0x8078
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#define QCA808X_MMD7_LED_CTRL(x) (0x8078 - ((x) * 2))
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#define QCA808X_MMD7_LED0_FORCE_CTRL 0x8079
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#define QCA808X_MMD7_LED_FORCE_CTRL(x) (0x8079 - ((x) * 2))
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#define QCA808X_MMD7_LED_POLARITY_CTRL 0x901a
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/* QSDK sets by default 0x46 to this reg that sets BIT 6 for
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* LED to active high. It's not clear what BIT 3 and BIT 4 does.
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*/
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#define QCA808X_LED_ACTIVE_HIGH BIT(6)
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/* QCA808X 1G chip type */
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#define QCA808X_PHY_MMD7_CHIP_TYPE 0x901d
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#define QCA808X_PHY_CHIP_TYPE_1G BIT(0)
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#define QCA8081_PHY_SERDES_MMD1_FIFO_CTRL 0x9072
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#define QCA8081_PHY_FIFO_RSTN BIT(11)
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#define QCA8081_PHY_ID 0x004dd101
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MODULE_DESCRIPTION("Qualcomm Atheros QCA808X PHY driver");
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MODULE_AUTHOR("Matus Ujhelyi");
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MODULE_LICENSE("GPL");
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struct qca808x_priv {
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int led_polarity_mode;
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};
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static int qca808x_phy_fast_retrain_config(struct phy_device *phydev)
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{
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int ret;
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/* Enable fast retrain */
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ret = genphy_c45_fast_retrain(phydev, true);
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if (ret)
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return ret;
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phy_write_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_TOP_OPTION1,
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QCA808X_TOP_OPTION1_DATA);
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phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB,
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QCA808X_MSE_THRESHOLD_20DB_VALUE);
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phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB,
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QCA808X_MSE_THRESHOLD_17DB_VALUE);
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phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB,
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QCA808X_MSE_THRESHOLD_27DB_VALUE);
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phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB,
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QCA808X_MSE_THRESHOLD_28DB_VALUE);
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phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_1,
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QCA808X_MMD3_DEBUG_1_VALUE);
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phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_4,
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QCA808X_MMD3_DEBUG_4_VALUE);
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phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_5,
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QCA808X_MMD3_DEBUG_5_VALUE);
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phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_3,
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QCA808X_MMD3_DEBUG_3_VALUE);
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phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_6,
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QCA808X_MMD3_DEBUG_6_VALUE);
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phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_2,
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QCA808X_MMD3_DEBUG_2_VALUE);
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return 0;
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}
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static int qca808x_phy_ms_seed_enable(struct phy_device *phydev, bool enable)
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{
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u16 seed_value;
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if (!enable)
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return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED,
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QCA808X_MASTER_SLAVE_SEED_ENABLE, 0);
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seed_value = get_random_u32_below(QCA808X_MASTER_SLAVE_SEED_RANGE);
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return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED,
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QCA808X_MASTER_SLAVE_SEED_CFG | QCA808X_MASTER_SLAVE_SEED_ENABLE,
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FIELD_PREP(QCA808X_MASTER_SLAVE_SEED_CFG, seed_value) |
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QCA808X_MASTER_SLAVE_SEED_ENABLE);
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}
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static bool qca808x_is_prefer_master(struct phy_device *phydev)
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{
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return (phydev->master_slave_get == MASTER_SLAVE_CFG_MASTER_FORCE) ||
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(phydev->master_slave_get == MASTER_SLAVE_CFG_MASTER_PREFERRED);
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}
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static bool qca808x_has_fast_retrain_or_slave_seed(struct phy_device *phydev)
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{
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return linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported);
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}
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static bool qca808x_is_1g_only(struct phy_device *phydev)
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{
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int ret;
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ret = phy_read_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_CHIP_TYPE);
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if (ret < 0)
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return true;
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return !!(QCA808X_PHY_CHIP_TYPE_1G & ret);
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}
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static void qca808x_fill_possible_interfaces(struct phy_device *phydev)
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{
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unsigned long *possible = phydev->possible_interfaces;
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__set_bit(PHY_INTERFACE_MODE_SGMII, possible);
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if (!qca808x_is_1g_only(phydev))
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__set_bit(PHY_INTERFACE_MODE_2500BASEX, possible);
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}
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static int qca808x_probe(struct phy_device *phydev)
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{
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struct device *dev = &phydev->mdio.dev;
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struct qca808x_priv *priv;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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/* Init LED polarity mode to -1 */
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priv->led_polarity_mode = -1;
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phydev->priv = priv;
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return 0;
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}
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static int qca808x_config_init(struct phy_device *phydev)
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{
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struct qca808x_priv *priv = phydev->priv;
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int ret;
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/* Default to LED Active High if active-low not in DT */
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if (priv->led_polarity_mode == -1) {
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ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN,
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QCA808X_MMD7_LED_POLARITY_CTRL,
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QCA808X_LED_ACTIVE_HIGH);
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if (ret)
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return ret;
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}
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/* Active adc&vga on 802.3az for the link 1000M and 100M */
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ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_ADDR_CLD_CTRL7,
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QCA808X_8023AZ_AFE_CTRL_MASK, QCA808X_8023AZ_AFE_EN);
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if (ret)
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return ret;
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/* Adjust the threshold on 802.3az for the link 1000M */
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ret = phy_write_mmd(phydev, MDIO_MMD_PCS,
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QCA808X_PHY_MMD3_AZ_TRAINING_CTRL,
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QCA808X_MMD3_AZ_TRAINING_VAL);
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if (ret)
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return ret;
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if (qca808x_has_fast_retrain_or_slave_seed(phydev)) {
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/* Config the fast retrain for the link 2500M */
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ret = qca808x_phy_fast_retrain_config(phydev);
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if (ret)
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return ret;
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ret = genphy_read_master_slave(phydev);
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if (ret < 0)
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return ret;
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if (!qca808x_is_prefer_master(phydev)) {
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/* Enable seed and configure lower ramdom seed to make phy
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* linked as slave mode.
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*/
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ret = qca808x_phy_ms_seed_enable(phydev, true);
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if (ret)
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return ret;
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}
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}
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qca808x_fill_possible_interfaces(phydev);
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/* Configure adc threshold as 100mv for the link 10M */
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return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_ADC_THRESHOLD,
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QCA808X_ADC_THRESHOLD_MASK,
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QCA808X_ADC_THRESHOLD_100MV);
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}
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static int qca808x_read_status(struct phy_device *phydev)
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{
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struct at803x_ss_mask ss_mask = { 0 };
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int ret;
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ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT);
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if (ret < 0)
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return ret;
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linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->lp_advertising,
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ret & MDIO_AN_10GBT_STAT_LP2_5G);
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ret = genphy_read_status(phydev);
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if (ret)
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return ret;
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/* qca8081 takes the different bits for speed value from at803x */
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ss_mask.speed_mask = QCA808X_SS_SPEED_MASK;
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ss_mask.speed_shift = __bf_shf(QCA808X_SS_SPEED_MASK);
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ret = at803x_read_specific_status(phydev, ss_mask);
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if (ret < 0)
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return ret;
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if (phydev->link) {
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if (phydev->speed == SPEED_2500)
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phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
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else
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phydev->interface = PHY_INTERFACE_MODE_SGMII;
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} else {
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/* generate seed as a lower random value to make PHY linked as SLAVE easily,
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* except for master/slave configuration fault detected or the master mode
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* preferred.
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*
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* the reason for not putting this code into the function link_change_notify is
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* the corner case where the link partner is also the qca8081 PHY and the seed
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* value is configured as the same value, the link can't be up and no link change
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* occurs.
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*/
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if (qca808x_has_fast_retrain_or_slave_seed(phydev)) {
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if (phydev->master_slave_state == MASTER_SLAVE_STATE_ERR ||
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qca808x_is_prefer_master(phydev)) {
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qca808x_phy_ms_seed_enable(phydev, false);
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} else {
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qca808x_phy_ms_seed_enable(phydev, true);
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}
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}
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}
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return 0;
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}
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static int qca808x_soft_reset(struct phy_device *phydev)
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{
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int ret;
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ret = genphy_soft_reset(phydev);
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if (ret < 0)
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return ret;
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if (qca808x_has_fast_retrain_or_slave_seed(phydev))
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ret = qca808x_phy_ms_seed_enable(phydev, true);
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return ret;
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}
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static int qca808x_cable_test_start(struct phy_device *phydev)
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{
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int ret;
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/* perform CDT with the following configs:
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* 1. disable hibernation.
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* 2. force PHY working in MDI mode.
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* 3. for PHY working in 1000BaseT.
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* 4. configure the threshold.
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*/
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ret = at803x_debug_reg_mask(phydev, QCA808X_DBG_AN_TEST, QCA808X_HIBERNATION_EN, 0);
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if (ret < 0)
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return ret;
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ret = at803x_config_mdix(phydev, ETH_TP_MDI);
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if (ret < 0)
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return ret;
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/* Force 1000base-T needs to configure PMA/PMD and MII_BMCR */
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phydev->duplex = DUPLEX_FULL;
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phydev->speed = SPEED_1000;
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ret = genphy_c45_pma_setup_forced(phydev);
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if (ret < 0)
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return ret;
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ret = genphy_setup_forced(phydev);
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if (ret < 0)
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return ret;
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/* configure the thresholds for open, short, pair ok test */
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phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8074, 0xc040);
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phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8076, 0xc040);
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phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8077, 0xa060);
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phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8078, 0xc050);
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phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807a, 0xc060);
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phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807e, 0xb060);
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return 0;
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}
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static int qca808x_get_features(struct phy_device *phydev)
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{
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int ret;
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ret = genphy_c45_pma_read_abilities(phydev);
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if (ret)
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return ret;
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/* The autoneg ability is not existed in bit3 of MMD7.1,
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* but it is supported by qca808x PHY, so we add it here
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* manually.
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*/
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linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported);
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/* As for the qca8081 1G version chip, the 2500baseT ability is also
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* existed in the bit0 of MMD1.21, we need to remove it manually if
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* it is the qca8081 1G chip according to the bit0 of MMD7.0x901d.
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*/
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if (qca808x_is_1g_only(phydev))
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linkmode_clear_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported);
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return 0;
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}
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static int qca808x_config_aneg(struct phy_device *phydev)
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{
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int phy_ctrl = 0;
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int ret;
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ret = at803x_prepare_config_aneg(phydev);
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if (ret)
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return ret;
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/* The reg MII_BMCR also needs to be configured for force mode, the
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* genphy_config_aneg is also needed.
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*/
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if (phydev->autoneg == AUTONEG_DISABLE)
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genphy_c45_pma_setup_forced(phydev);
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if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->advertising))
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phy_ctrl = MDIO_AN_10GBT_CTRL_ADV2_5G;
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ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
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MDIO_AN_10GBT_CTRL_ADV2_5G, phy_ctrl);
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if (ret < 0)
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return ret;
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return __genphy_config_aneg(phydev, ret);
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}
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static void qca808x_link_change_notify(struct phy_device *phydev)
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{
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/* Assert interface sgmii fifo on link down, deassert it on link up,
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* the interface device address is always phy address added by 1.
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*/
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mdiobus_c45_modify_changed(phydev->mdio.bus, phydev->mdio.addr + 1,
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MDIO_MMD_PMAPMD, QCA8081_PHY_SERDES_MMD1_FIFO_CTRL,
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QCA8081_PHY_FIFO_RSTN,
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phydev->link ? QCA8081_PHY_FIFO_RSTN : 0);
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}
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static int qca808x_led_parse_netdev(struct phy_device *phydev, unsigned long rules,
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u16 *offload_trigger)
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{
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/* Parsing specific to netdev trigger */
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if (test_bit(TRIGGER_NETDEV_TX, &rules))
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*offload_trigger |= QCA808X_LED_TX_BLINK;
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if (test_bit(TRIGGER_NETDEV_RX, &rules))
|
|
*offload_trigger |= QCA808X_LED_RX_BLINK;
|
|
if (test_bit(TRIGGER_NETDEV_LINK_10, &rules))
|
|
*offload_trigger |= QCA808X_LED_SPEED10_ON;
|
|
if (test_bit(TRIGGER_NETDEV_LINK_100, &rules))
|
|
*offload_trigger |= QCA808X_LED_SPEED100_ON;
|
|
if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules))
|
|
*offload_trigger |= QCA808X_LED_SPEED1000_ON;
|
|
if (test_bit(TRIGGER_NETDEV_LINK_2500, &rules))
|
|
*offload_trigger |= QCA808X_LED_SPEED2500_ON;
|
|
if (test_bit(TRIGGER_NETDEV_HALF_DUPLEX, &rules))
|
|
*offload_trigger |= QCA808X_LED_HALF_DUPLEX_ON;
|
|
if (test_bit(TRIGGER_NETDEV_FULL_DUPLEX, &rules))
|
|
*offload_trigger |= QCA808X_LED_FULL_DUPLEX_ON;
|
|
|
|
if (rules && !*offload_trigger)
|
|
return -EOPNOTSUPP;
|
|
|
|
/* Enable BLINK_CHECK_BYPASS by default to make the LED
|
|
* blink even with duplex or speed mode not enabled.
|
|
*/
|
|
*offload_trigger |= QCA808X_LED_BLINK_CHECK_BYPASS;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int qca808x_led_hw_control_enable(struct phy_device *phydev, u8 index)
|
|
{
|
|
u16 reg;
|
|
|
|
if (index > 2)
|
|
return -EINVAL;
|
|
|
|
reg = QCA808X_MMD7_LED_FORCE_CTRL(index);
|
|
return qca808x_led_reg_hw_control_enable(phydev, reg);
|
|
}
|
|
|
|
static int qca808x_led_hw_is_supported(struct phy_device *phydev, u8 index,
|
|
unsigned long rules)
|
|
{
|
|
u16 offload_trigger = 0;
|
|
|
|
if (index > 2)
|
|
return -EINVAL;
|
|
|
|
return qca808x_led_parse_netdev(phydev, rules, &offload_trigger);
|
|
}
|
|
|
|
static int qca808x_led_hw_control_set(struct phy_device *phydev, u8 index,
|
|
unsigned long rules)
|
|
{
|
|
u16 reg, offload_trigger = 0;
|
|
int ret;
|
|
|
|
if (index > 2)
|
|
return -EINVAL;
|
|
|
|
reg = QCA808X_MMD7_LED_CTRL(index);
|
|
|
|
ret = qca808x_led_parse_netdev(phydev, rules, &offload_trigger);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = qca808x_led_hw_control_enable(phydev, index);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return phy_modify_mmd(phydev, MDIO_MMD_AN, reg,
|
|
QCA808X_LED_PATTERN_MASK,
|
|
offload_trigger);
|
|
}
|
|
|
|
static bool qca808x_led_hw_control_status(struct phy_device *phydev, u8 index)
|
|
{
|
|
u16 reg;
|
|
|
|
if (index > 2)
|
|
return false;
|
|
|
|
reg = QCA808X_MMD7_LED_FORCE_CTRL(index);
|
|
return qca808x_led_reg_hw_control_status(phydev, reg);
|
|
}
|
|
|
|
static int qca808x_led_hw_control_get(struct phy_device *phydev, u8 index,
|
|
unsigned long *rules)
|
|
{
|
|
u16 reg;
|
|
int val;
|
|
|
|
if (index > 2)
|
|
return -EINVAL;
|
|
|
|
/* Check if we have hw control enabled */
|
|
if (qca808x_led_hw_control_status(phydev, index))
|
|
return -EINVAL;
|
|
|
|
reg = QCA808X_MMD7_LED_CTRL(index);
|
|
|
|
val = phy_read_mmd(phydev, MDIO_MMD_AN, reg);
|
|
if (val & QCA808X_LED_TX_BLINK)
|
|
set_bit(TRIGGER_NETDEV_TX, rules);
|
|
if (val & QCA808X_LED_RX_BLINK)
|
|
set_bit(TRIGGER_NETDEV_RX, rules);
|
|
if (val & QCA808X_LED_SPEED10_ON)
|
|
set_bit(TRIGGER_NETDEV_LINK_10, rules);
|
|
if (val & QCA808X_LED_SPEED100_ON)
|
|
set_bit(TRIGGER_NETDEV_LINK_100, rules);
|
|
if (val & QCA808X_LED_SPEED1000_ON)
|
|
set_bit(TRIGGER_NETDEV_LINK_1000, rules);
|
|
if (val & QCA808X_LED_SPEED2500_ON)
|
|
set_bit(TRIGGER_NETDEV_LINK_2500, rules);
|
|
if (val & QCA808X_LED_HALF_DUPLEX_ON)
|
|
set_bit(TRIGGER_NETDEV_HALF_DUPLEX, rules);
|
|
if (val & QCA808X_LED_FULL_DUPLEX_ON)
|
|
set_bit(TRIGGER_NETDEV_FULL_DUPLEX, rules);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int qca808x_led_hw_control_reset(struct phy_device *phydev, u8 index)
|
|
{
|
|
u16 reg;
|
|
|
|
if (index > 2)
|
|
return -EINVAL;
|
|
|
|
reg = QCA808X_MMD7_LED_CTRL(index);
|
|
|
|
return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg,
|
|
QCA808X_LED_PATTERN_MASK);
|
|
}
|
|
|
|
static int qca808x_led_brightness_set(struct phy_device *phydev,
|
|
u8 index, enum led_brightness value)
|
|
{
|
|
u16 reg;
|
|
int ret;
|
|
|
|
if (index > 2)
|
|
return -EINVAL;
|
|
|
|
if (!value) {
|
|
ret = qca808x_led_hw_control_reset(phydev, index);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
reg = QCA808X_MMD7_LED_FORCE_CTRL(index);
|
|
return qca808x_led_reg_brightness_set(phydev, reg, value);
|
|
}
|
|
|
|
static int qca808x_led_blink_set(struct phy_device *phydev, u8 index,
|
|
unsigned long *delay_on,
|
|
unsigned long *delay_off)
|
|
{
|
|
u16 reg;
|
|
|
|
if (index > 2)
|
|
return -EINVAL;
|
|
|
|
reg = QCA808X_MMD7_LED_FORCE_CTRL(index);
|
|
return qca808x_led_reg_blink_set(phydev, reg, delay_on, delay_off);
|
|
}
|
|
|
|
static int qca808x_led_polarity_set(struct phy_device *phydev, int index,
|
|
unsigned long modes)
|
|
{
|
|
struct qca808x_priv *priv = phydev->priv;
|
|
bool active_low = false;
|
|
u32 mode;
|
|
|
|
for_each_set_bit(mode, &modes, __PHY_LED_MODES_NUM) {
|
|
switch (mode) {
|
|
case PHY_LED_ACTIVE_LOW:
|
|
active_low = true;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
|
|
/* PHY polarity is global and can't be set per LED.
|
|
* To detect this, check if last requested polarity mode
|
|
* match the new one.
|
|
*/
|
|
if (priv->led_polarity_mode >= 0 &&
|
|
priv->led_polarity_mode != active_low) {
|
|
phydev_err(phydev, "PHY polarity is global. Mismatched polarity on different LED\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* Save the last PHY polarity mode */
|
|
priv->led_polarity_mode = active_low;
|
|
|
|
return phy_modify_mmd(phydev, MDIO_MMD_AN,
|
|
QCA808X_MMD7_LED_POLARITY_CTRL,
|
|
QCA808X_LED_ACTIVE_HIGH,
|
|
active_low ? 0 : QCA808X_LED_ACTIVE_HIGH);
|
|
}
|
|
|
|
static struct phy_driver qca808x_driver[] = {
|
|
{
|
|
/* Qualcomm QCA8081 */
|
|
PHY_ID_MATCH_EXACT(QCA8081_PHY_ID),
|
|
.name = "Qualcomm QCA8081",
|
|
.flags = PHY_POLL_CABLE_TEST,
|
|
.probe = qca808x_probe,
|
|
.config_intr = at803x_config_intr,
|
|
.handle_interrupt = at803x_handle_interrupt,
|
|
.get_tunable = at803x_get_tunable,
|
|
.set_tunable = at803x_set_tunable,
|
|
.set_wol = at803x_set_wol,
|
|
.get_wol = at803x_get_wol,
|
|
.get_features = qca808x_get_features,
|
|
.config_aneg = qca808x_config_aneg,
|
|
.suspend = genphy_suspend,
|
|
.resume = genphy_resume,
|
|
.read_status = qca808x_read_status,
|
|
.config_init = qca808x_config_init,
|
|
.soft_reset = qca808x_soft_reset,
|
|
.cable_test_start = qca808x_cable_test_start,
|
|
.cable_test_get_status = qca808x_cable_test_get_status,
|
|
.link_change_notify = qca808x_link_change_notify,
|
|
.led_brightness_set = qca808x_led_brightness_set,
|
|
.led_blink_set = qca808x_led_blink_set,
|
|
.led_hw_is_supported = qca808x_led_hw_is_supported,
|
|
.led_hw_control_set = qca808x_led_hw_control_set,
|
|
.led_hw_control_get = qca808x_led_hw_control_get,
|
|
.led_polarity_set = qca808x_led_polarity_set,
|
|
}, };
|
|
|
|
module_phy_driver(qca808x_driver);
|
|
|
|
static struct mdio_device_id __maybe_unused qca808x_tbl[] = {
|
|
{ PHY_ID_MATCH_EXACT(QCA8081_PHY_ID) },
|
|
{ }
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(mdio, qca808x_tbl);
|