143 lines
3.4 KiB
C
143 lines
3.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/* Copyright (c) Tehuti Networks Ltd. */
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#include <linux/netdevice.h>
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#include <linux/pci.h>
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#include <linux/phylink.h>
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#include "tn40.h"
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#define TN40_MDIO_DEVAD_MASK GENMASK(4, 0)
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#define TN40_MDIO_PRTAD_MASK GENMASK(9, 5)
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#define TN40_MDIO_CMD_VAL(device, port) \
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(FIELD_PREP(TN40_MDIO_DEVAD_MASK, (device)) | \
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(FIELD_PREP(TN40_MDIO_PRTAD_MASK, (port))))
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#define TN40_MDIO_CMD_READ BIT(15)
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static void tn40_mdio_set_speed(struct tn40_priv *priv, u32 speed)
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{
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void __iomem *regs = priv->regs;
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int mdio_cfg;
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if (speed == TN40_MDIO_SPEED_1MHZ)
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mdio_cfg = (0x7d << 7) | 0x08; /* 1MHz */
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else
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mdio_cfg = 0xA08; /* 6MHz */
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mdio_cfg |= (1 << 6);
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writel(mdio_cfg, regs + TN40_REG_MDIO_CMD_STAT);
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msleep(100);
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}
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static u32 tn40_mdio_stat(struct tn40_priv *priv)
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{
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void __iomem *regs = priv->regs;
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return readl(regs + TN40_REG_MDIO_CMD_STAT);
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}
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static int tn40_mdio_wait_nobusy(struct tn40_priv *priv, u32 *val)
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{
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u32 stat;
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int ret;
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ret = readx_poll_timeout_atomic(tn40_mdio_stat, priv, stat,
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TN40_GET_MDIO_BUSY(stat) == 0, 10,
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10000);
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if (val)
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*val = stat;
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return ret;
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}
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static int tn40_mdio_read(struct tn40_priv *priv, int port, int device,
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u16 regnum)
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{
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void __iomem *regs = priv->regs;
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u32 i;
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/* wait until MDIO is not busy */
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if (tn40_mdio_wait_nobusy(priv, NULL))
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return -EIO;
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i = TN40_MDIO_CMD_VAL(device, port);
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writel(i, regs + TN40_REG_MDIO_CMD);
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writel((u32)regnum, regs + TN40_REG_MDIO_ADDR);
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if (tn40_mdio_wait_nobusy(priv, NULL))
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return -EIO;
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writel(TN40_MDIO_CMD_READ | i, regs + TN40_REG_MDIO_CMD);
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/* read CMD_STAT until not busy */
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if (tn40_mdio_wait_nobusy(priv, NULL))
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return -EIO;
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return lower_16_bits(readl(regs + TN40_REG_MDIO_DATA));
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}
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static int tn40_mdio_write(struct tn40_priv *priv, int port, int device,
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u16 regnum, u16 data)
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{
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void __iomem *regs = priv->regs;
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u32 tmp_reg = 0;
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int ret;
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/* wait until MDIO is not busy */
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if (tn40_mdio_wait_nobusy(priv, NULL))
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return -EIO;
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writel(TN40_MDIO_CMD_VAL(device, port), regs + TN40_REG_MDIO_CMD);
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writel((u32)regnum, regs + TN40_REG_MDIO_ADDR);
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if (tn40_mdio_wait_nobusy(priv, NULL))
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return -EIO;
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writel((u32)data, regs + TN40_REG_MDIO_DATA);
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/* read CMD_STAT until not busy */
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ret = tn40_mdio_wait_nobusy(priv, &tmp_reg);
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if (ret)
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return -EIO;
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if (TN40_GET_MDIO_RD_ERR(tmp_reg)) {
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dev_err(&priv->pdev->dev, "MDIO error after write command\n");
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return -EIO;
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}
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return 0;
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}
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static int tn40_mdio_read_c45(struct mii_bus *mii_bus, int addr, int devnum,
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int regnum)
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{
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return tn40_mdio_read(mii_bus->priv, addr, devnum, regnum);
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}
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static int tn40_mdio_write_c45(struct mii_bus *mii_bus, int addr, int devnum,
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int regnum, u16 val)
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{
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return tn40_mdio_write(mii_bus->priv, addr, devnum, regnum, val);
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}
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int tn40_mdiobus_init(struct tn40_priv *priv)
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{
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struct pci_dev *pdev = priv->pdev;
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struct mii_bus *bus;
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int ret;
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bus = devm_mdiobus_alloc(&pdev->dev);
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if (!bus)
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return -ENOMEM;
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bus->name = TN40_DRV_NAME;
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bus->parent = &pdev->dev;
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snprintf(bus->id, MII_BUS_ID_SIZE, "tn40xx-%x-%x",
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pci_domain_nr(pdev->bus), pci_dev_id(pdev));
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bus->priv = priv;
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bus->read_c45 = tn40_mdio_read_c45;
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bus->write_c45 = tn40_mdio_write_c45;
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ret = devm_mdiobus_register(&pdev->dev, bus);
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if (ret) {
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dev_err(&pdev->dev, "failed to register mdiobus %d %u %u\n",
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ret, bus->state, MDIOBUS_UNREGISTERED);
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return ret;
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}
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tn40_mdio_set_speed(priv, TN40_MDIO_SPEED_6MHZ);
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priv->mdio = bus;
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return 0;
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}
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