346 lines
9.2 KiB
C
346 lines
9.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
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/*
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* rtase is the Linux device driver released for Realtek Automotive Switch
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* controllers with PCI-Express interface.
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*
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* Copyright(c) 2024 Realtek Semiconductor Corp.
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*/
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#ifndef RTASE_H
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#define RTASE_H
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#define RTASE_HW_VER_MASK 0x7C800000
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#define RTASE_HW_VER_906X_7XA 0x00800000
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#define RTASE_HW_VER_906X_7XC 0x04000000
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#define RTASE_HW_VER_907XD_V1 0x04800000
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#define RTASE_RX_DMA_BURST_256 4
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#define RTASE_TX_DMA_BURST_UNLIMITED 7
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#define RTASE_RX_BUF_SIZE (PAGE_SIZE - \
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SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
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#define RTASE_MAX_JUMBO_SIZE (RTASE_RX_BUF_SIZE - VLAN_ETH_HLEN - ETH_FCS_LEN)
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/* 3 means InterFrameGap = the shortest one */
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#define RTASE_INTERFRAMEGAP 0x03
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#define RTASE_REGS_SIZE 256
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#define RTASE_PCI_REGS_SIZE 0x100
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#define RTASE_MULTICAST_FILTER_MASK GENMASK(30, 26)
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#define RTASE_VLAN_FILTER_ENTRY_NUM 32
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#define RTASE_NUM_TX_QUEUE 8
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#define RTASE_NUM_RX_QUEUE 4
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#define RTASE_TXQ_CTRL 1
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#define RTASE_FUNC_TXQ_NUM 1
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#define RTASE_FUNC_RXQ_NUM 1
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#define RTASE_INTERRUPT_NUM 1
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#define RTASE_MITI_TIME_COUNT_MASK GENMASK(3, 0)
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#define RTASE_MITI_TIME_UNIT_MASK GENMASK(7, 4)
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#define RTASE_MITI_DEFAULT_TIME 128
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#define RTASE_MITI_MAX_TIME 491520
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#define RTASE_MITI_PKT_NUM_COUNT_MASK GENMASK(11, 8)
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#define RTASE_MITI_PKT_NUM_UNIT_MASK GENMASK(13, 12)
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#define RTASE_MITI_DEFAULT_PKT_NUM 64
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#define RTASE_MITI_MAX_PKT_NUM_IDX 3
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#define RTASE_MITI_MAX_PKT_NUM_UNIT 16
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#define RTASE_MITI_MAX_PKT_NUM 240
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#define RTASE_MITI_COUNT_BIT_NUM 4
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#define RTASE_NUM_MSIX 4
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#define RTASE_DWORD_MOD 16
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/*****************************************************************************/
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enum rtase_registers {
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RTASE_MAC0 = 0x0000,
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RTASE_MAC4 = 0x0004,
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RTASE_MAR0 = 0x0008,
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RTASE_MAR1 = 0x000C,
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RTASE_DTCCR0 = 0x0010,
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RTASE_DTCCR4 = 0x0014,
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#define RTASE_COUNTER_RESET BIT(0)
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#define RTASE_COUNTER_DUMP BIT(3)
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RTASE_FCR = 0x0018,
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#define RTASE_FCR_RXQ_MASK GENMASK(5, 4)
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RTASE_LBK_CTRL = 0x001A,
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#define RTASE_LBK_ATLD BIT(1)
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#define RTASE_LBK_CLR BIT(0)
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RTASE_TX_DESC_ADDR0 = 0x0020,
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RTASE_TX_DESC_ADDR4 = 0x0024,
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RTASE_TX_DESC_COMMAND = 0x0028,
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#define RTASE_TX_DESC_CMD_CS BIT(15)
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#define RTASE_TX_DESC_CMD_WE BIT(14)
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RTASE_BOOT_CTL = 0x6004,
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RTASE_CLKSW_SET = 0x6018,
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RTASE_CHIP_CMD = 0x0037,
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#define RTASE_STOP_REQ BIT(7)
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#define RTASE_STOP_REQ_DONE BIT(6)
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#define RTASE_RE BIT(3)
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#define RTASE_TE BIT(2)
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RTASE_IMR0 = 0x0038,
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RTASE_ISR0 = 0x003C,
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#define RTASE_TOK7 BIT(30)
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#define RTASE_TOK6 BIT(28)
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#define RTASE_TOK5 BIT(26)
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#define RTASE_TOK4 BIT(24)
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#define RTASE_FOVW BIT(6)
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#define RTASE_RDU BIT(4)
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#define RTASE_TOK BIT(2)
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#define RTASE_ROK BIT(0)
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RTASE_IMR1 = 0x0800,
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RTASE_ISR1 = 0x0802,
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#define RTASE_Q_TOK BIT(4)
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#define RTASE_Q_RDU BIT(1)
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#define RTASE_Q_ROK BIT(0)
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RTASE_EPHY_ISR = 0x6014,
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RTASE_EPHY_IMR = 0x6016,
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RTASE_TX_CONFIG_0 = 0x0040,
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#define RTASE_TX_INTER_FRAME_GAP_MASK GENMASK(25, 24)
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/* DMA burst value (0-7) is shift this many bits */
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#define RTASE_TX_DMA_MASK GENMASK(10, 8)
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RTASE_RX_CONFIG_0 = 0x0044,
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#define RTASE_RX_SINGLE_FETCH BIT(14)
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#define RTASE_RX_SINGLE_TAG BIT(13)
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#define RTASE_RX_MX_DMA_MASK GENMASK(10, 8)
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#define RTASE_ACPT_FLOW BIT(7)
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#define RTASE_ACCEPT_ERR BIT(5)
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#define RTASE_ACCEPT_RUNT BIT(4)
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#define RTASE_ACCEPT_BROADCAST BIT(3)
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#define RTASE_ACCEPT_MULTICAST BIT(2)
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#define RTASE_ACCEPT_MYPHYS BIT(1)
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#define RTASE_ACCEPT_ALLPHYS BIT(0)
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#define RTASE_ACCEPT_MASK (RTASE_ACPT_FLOW | RTASE_ACCEPT_ERR | \
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RTASE_ACCEPT_RUNT | RTASE_ACCEPT_BROADCAST | \
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RTASE_ACCEPT_MULTICAST | RTASE_ACCEPT_MYPHYS | \
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RTASE_ACCEPT_ALLPHYS)
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RTASE_RX_CONFIG_1 = 0x0046,
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#define RTASE_RX_MAX_FETCH_DESC_MASK GENMASK(15, 11)
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#define RTASE_RX_NEW_DESC_FORMAT_EN BIT(8)
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#define RTASE_OUTER_VLAN_DETAG_EN BIT(7)
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#define RTASE_INNER_VLAN_DETAG_EN BIT(6)
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#define RTASE_PCIE_NEW_FLOW BIT(2)
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#define RTASE_PCIE_RELOAD_EN BIT(0)
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RTASE_EEM = 0x0050,
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#define RTASE_EEM_UNLOCK 0xC0
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RTASE_TDFNR = 0x0057,
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RTASE_TPPOLL = 0x0090,
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RTASE_PDR = 0x00B0,
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RTASE_FIFOR = 0x00D3,
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#define RTASE_TX_FIFO_EMPTY BIT(5)
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#define RTASE_RX_FIFO_EMPTY BIT(4)
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RTASE_RMS = 0x00DA,
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RTASE_CPLUS_CMD = 0x00E0,
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#define RTASE_FORCE_RXFLOW_EN BIT(11)
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#define RTASE_FORCE_TXFLOW_EN BIT(10)
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#define RTASE_RX_CHKSUM BIT(5)
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RTASE_Q0_RX_DESC_ADDR0 = 0x00E4,
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RTASE_Q0_RX_DESC_ADDR4 = 0x00E8,
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RTASE_Q1_RX_DESC_ADDR0 = 0x4000,
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RTASE_Q1_RX_DESC_ADDR4 = 0x4004,
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RTASE_MTPS = 0x00EC,
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#define RTASE_TAG_NUM_SEL_MASK GENMASK(10, 8)
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RTASE_MISC = 0x00F2,
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#define RTASE_RX_DV_GATE_EN BIT(3)
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RTASE_TFUN_CTRL = 0x0400,
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#define RTASE_TX_NEW_DESC_FORMAT_EN BIT(0)
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RTASE_TX_CONFIG_1 = 0x203E,
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#define RTASE_TC_MODE_MASK GENMASK(11, 10)
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RTASE_TOKSEL = 0x2046,
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RTASE_RFIFONFULL = 0x4406,
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RTASE_INT_MITI_TX = 0x0A00,
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RTASE_INT_MITI_RX = 0x0A80,
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RTASE_VLAN_ENTRY_0 = 0xAC80,
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};
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enum rtase_desc_status_bit {
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RTASE_DESC_OWN = BIT(31), /* Descriptor is owned by NIC */
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RTASE_RING_END = BIT(30), /* End of descriptor ring */
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};
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enum rtase_sw_flag_content {
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RTASE_SWF_MSI_ENABLED = BIT(1),
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RTASE_SWF_MSIX_ENABLED = BIT(2),
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};
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#define RSVD_MASK 0x3FFFC000
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struct rtase_tx_desc {
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__le32 opts1;
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__le32 opts2;
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__le64 addr;
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__le32 opts3;
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__le32 reserved1;
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__le32 reserved2;
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__le32 reserved3;
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} __packed;
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/*------ offset 0 of tx descriptor ------*/
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#define RTASE_TX_FIRST_FRAG BIT(29) /* Tx First segment of a packet */
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#define RTASE_TX_LAST_FRAG BIT(28) /* Tx Final segment of a packet */
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#define RTASE_GIANT_SEND_V4 BIT(26) /* TCP Giant Send Offload V4 (GSOv4) */
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#define RTASE_GIANT_SEND_V6 BIT(25) /* TCP Giant Send Offload V6 (GSOv6) */
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#define RTASE_TX_VLAN_TAG BIT(17) /* Add VLAN tag */
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/*------ offset 4 of tx descriptor ------*/
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#define RTASE_TX_UDPCS_C BIT(31) /* Calculate UDP/IP checksum */
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#define RTASE_TX_TCPCS_C BIT(30) /* Calculate TCP/IP checksum */
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#define RTASE_TX_IPCS_C BIT(29) /* Calculate IP checksum */
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#define RTASE_TX_IPV6F_C BIT(28) /* Indicate it is an IPv6 packet */
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union rtase_rx_desc {
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struct {
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__le64 header_buf_addr;
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__le32 reserved1;
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__le32 opts_header_len;
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__le64 addr;
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__le32 reserved2;
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__le32 opts1;
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} __packed desc_cmd;
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struct {
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__le32 reserved1;
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__le32 reserved2;
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__le32 rss;
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__le32 opts4;
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__le32 reserved3;
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__le32 opts3;
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__le32 opts2;
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__le32 opts1;
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} __packed desc_status;
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} __packed;
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/*------ offset 28 of rx descriptor ------*/
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#define RTASE_RX_FIRST_FRAG BIT(25) /* Rx First segment of a packet */
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#define RTASE_RX_LAST_FRAG BIT(24) /* Rx Final segment of a packet */
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#define RTASE_RX_RES BIT(20)
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#define RTASE_RX_RUNT BIT(19)
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#define RTASE_RX_RWT BIT(18)
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#define RTASE_RX_CRC BIT(16)
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#define RTASE_RX_V6F BIT(31)
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#define RTASE_RX_V4F BIT(30)
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#define RTASE_RX_UDPT BIT(29)
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#define RTASE_RX_TCPT BIT(28)
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#define RTASE_RX_IPF BIT(26) /* IP checksum failed */
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#define RTASE_RX_UDPF BIT(25) /* UDP/IP checksum failed */
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#define RTASE_RX_TCPF BIT(24) /* TCP/IP checksum failed */
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#define RTASE_RX_VLAN_TAG BIT(16) /* VLAN tag available */
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#define RTASE_NUM_DESC 1024
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#define RTASE_TX_BUDGET_DEFAULT 256
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#define RTASE_TX_RING_DESC_SIZE (RTASE_NUM_DESC * sizeof(struct rtase_tx_desc))
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#define RTASE_RX_RING_DESC_SIZE (RTASE_NUM_DESC * sizeof(union rtase_rx_desc))
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#define RTASE_TX_STOP_THRS (MAX_SKB_FRAGS + 1)
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#define RTASE_TX_START_THRS (2 * RTASE_TX_STOP_THRS)
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#define RTASE_VLAN_TAG_MASK GENMASK(15, 0)
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#define RTASE_RX_PKT_SIZE_MASK GENMASK(13, 0)
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#define RTASE_IVEC_NAME_SIZE (IFNAMSIZ + 10)
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struct rtase_int_vector {
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struct rtase_private *tp;
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unsigned int irq;
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char name[RTASE_IVEC_NAME_SIZE];
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u16 index;
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u16 imr_addr;
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u16 isr_addr;
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u32 imr;
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struct list_head ring_list;
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struct napi_struct napi;
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int (*poll)(struct napi_struct *napi, int budget);
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};
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struct rtase_ring {
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struct rtase_int_vector *ivec;
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void *desc;
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dma_addr_t phy_addr;
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u32 cur_idx;
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u32 dirty_idx;
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u16 index;
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struct sk_buff *skbuff[RTASE_NUM_DESC];
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void *data_buf[RTASE_NUM_DESC];
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union {
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u32 len[RTASE_NUM_DESC];
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dma_addr_t data_phy_addr[RTASE_NUM_DESC];
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} mis;
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struct list_head ring_entry;
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int (*ring_handler)(struct rtase_ring *ring, int budget);
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u64 alloc_fail;
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};
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struct rtase_stats {
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u64 tx_dropped;
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u64 rx_dropped;
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u64 multicast;
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u64 rx_errors;
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u64 rx_length_errors;
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u64 rx_crc_errors;
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};
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struct rtase_private {
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void __iomem *mmio_addr;
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u32 sw_flag;
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struct pci_dev *pdev;
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struct net_device *dev;
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u32 rx_buf_sz;
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struct page_pool *page_pool;
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struct rtase_ring tx_ring[RTASE_NUM_TX_QUEUE];
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struct rtase_ring rx_ring[RTASE_NUM_RX_QUEUE];
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struct rtase_counters *tally_vaddr;
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dma_addr_t tally_paddr;
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u32 vlan_filter_ctrl;
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u16 vlan_filter_vid[RTASE_VLAN_FILTER_ENTRY_NUM];
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struct msix_entry msix_entry[RTASE_NUM_MSIX];
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struct rtase_int_vector int_vector[RTASE_NUM_MSIX];
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struct rtase_stats stats;
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u16 tx_queue_ctrl;
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u16 func_tx_queue_num;
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u16 func_rx_queue_num;
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u16 int_nums;
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u16 tx_int_mit;
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u16 rx_int_mit;
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u32 hw_ver;
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};
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#define RTASE_LSO_64K 64000
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#define RTASE_NIC_MAX_PHYS_BUF_COUNT_LSO2 (16 * 4)
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#define RTASE_TCPHO_MASK GENMASK(24, 18)
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#define RTASE_MSS_MASK GENMASK(28, 18)
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#endif /* RTASE_H */
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