103 lines
3.7 KiB
C
103 lines
3.7 KiB
C
/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
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/*
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* Wave5 series multi-standard codec IP - product config definitions
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*
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* Copyright (C) 2021-2023 CHIPS&MEDIA INC
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*/
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#ifndef _VPU_CONFIG_H_
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#define _VPU_CONFIG_H_
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#define WAVE515_CODE 0x5150
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#define WAVE517_CODE 0x5170
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#define WAVE537_CODE 0x5370
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#define WAVE511_CODE 0x5110
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#define WAVE521_CODE 0x5210
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#define WAVE521C_CODE 0x521c
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#define WAVE521C_DUAL_CODE 0x521d // wave521 dual core
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#define WAVE521E1_CODE 0x5211
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#define PRODUCT_CODE_W_SERIES(x) ({ \
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int c = x; \
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((c) == WAVE517_CODE || (c) == WAVE537_CODE || \
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(c) == WAVE511_CODE || (c) == WAVE521_CODE || \
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(c) == WAVE521E1_CODE || (c) == WAVE521C_CODE || \
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(c) == WAVE521C_DUAL_CODE) || (c) == WAVE515_CODE; \
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})
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#define WAVE517_WORKBUF_SIZE (2 * 1024 * 1024)
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#define WAVE521ENC_WORKBUF_SIZE (128 * 1024) //HEVC 128K, AVC 40K
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#define WAVE521DEC_WORKBUF_SIZE (1784 * 1024)
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#define WAVE515DEC_WORKBUF_SIZE (2 * 1024 * 1024)
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#define MAX_NUM_INSTANCE 32
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#define W5_DEF_DEC_PIC_WIDTH 720U
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#define W5_DEF_DEC_PIC_HEIGHT 480U
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#define W5_MIN_DEC_PIC_8_WIDTH 8U
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#define W5_MIN_DEC_PIC_8_HEIGHT 8U
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#define W5_MIN_DEC_PIC_32_WIDTH 32U
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#define W5_MIN_DEC_PIC_32_HEIGHT 32U
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#define W5_MAX_DEC_PIC_WIDTH 8192U
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#define W5_MAX_DEC_PIC_HEIGHT 4320U
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#define W5_DEC_CODEC_STEP_WIDTH 1U
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#define W5_DEC_CODEC_STEP_HEIGHT 1U
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#define W5_DEC_RAW_STEP_WIDTH 32U
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#define W5_DEC_RAW_STEP_HEIGHT 16U
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#define W5_DEF_ENC_PIC_WIDTH 416U
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#define W5_DEF_ENC_PIC_HEIGHT 240U
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#define W5_MIN_ENC_PIC_WIDTH 256U
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#define W5_MIN_ENC_PIC_HEIGHT 128U
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#define W5_MAX_ENC_PIC_WIDTH 8192U
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#define W5_MAX_ENC_PIC_HEIGHT 8192U
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#define W5_ENC_CODEC_STEP_WIDTH 8U
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#define W5_ENC_CODEC_STEP_HEIGHT 8U
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#define W5_ENC_RAW_STEP_WIDTH 32U
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#define W5_ENC_RAW_STEP_HEIGHT 16U
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// application specific configuration
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#define VPU_ENC_TIMEOUT 60000
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#define VPU_DEC_TIMEOUT 60000
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// for WAVE encoder
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#define USE_SRC_PRP_AXI 0
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#define USE_SRC_PRI_AXI 1
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#define DEFAULT_SRC_AXI USE_SRC_PRP_AXI
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/************************************************************************/
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/* VPU COMMON MEMORY */
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/************************************************************************/
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#define VLC_BUF_NUM (2)
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#define WAVE521_COMMAND_QUEUE_DEPTH (2)
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#define WAVE515_COMMAND_QUEUE_DEPTH (4)
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#define W5_REMAP_INDEX0 0
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#define W5_REMAP_INDEX1 1
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#define W5_REMAP_MAX_SIZE (1024 * 1024)
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#define WAVE521_MAX_CODE_BUF_SIZE (2 * 1024 * 1024)
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#define WAVE515_MAX_CODE_BUF_SIZE (1024 * 1024)
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#define WAVE5_TEMPBUF_SIZE (1024 * 1024)
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#define WAVE521_SIZE_COMMON (WAVE521_MAX_CODE_BUF_SIZE + WAVE5_TEMPBUF_SIZE)
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#define WAVE515_ONE_TASKBUF_SIZE (8 * 1024 * 1024)
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#define WAVE515_SIZE_COMMON (WAVE515_MAX_CODE_BUF_SIZE + WAVE5_TEMPBUF_SIZE + \
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WAVE515_COMMAND_QUEUE_DEPTH * WAVE515_ONE_TASKBUF_SIZE)
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//=====4. VPU REPORT MEMORY ======================//
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#define WAVE5_UPPER_PROC_AXI_ID 0x0
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#define WAVE5_PROC_AXI_ID 0x0
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#define WAVE5_PRP_AXI_ID 0x0
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#define WAVE5_FBD_Y_AXI_ID 0x0
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#define WAVE5_FBC_Y_AXI_ID 0x0
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#define WAVE5_FBD_C_AXI_ID 0x0
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#define WAVE5_FBC_C_AXI_ID 0x0
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#define WAVE5_SEC_AXI_ID 0x0
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#define WAVE5_PRI_AXI_ID 0x0
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#endif /* _VPU_CONFIG_H_ */
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