140 lines
4.0 KiB
C
140 lines
4.0 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2023 Intel Corporation
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*/
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#ifndef _XE_REG_DEFS_H_
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#define _XE_REG_DEFS_H_
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#include <linux/build_bug.h>
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#include "compat-i915-headers/i915_reg_defs.h"
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/**
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* struct xe_reg - Register definition
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*
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* Register defintion to be used by the individual register. Although the same
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* definition is used for xe_reg and xe_reg_mcr, they use different internal
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* APIs for accesses.
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*/
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struct xe_reg {
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union {
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struct {
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/** @addr: address */
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u32 addr:28;
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/**
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* @masked: register is "masked", with upper 16bits used
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* to identify the bits that are updated on the lower
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* bits
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*/
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u32 masked:1;
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/**
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* @mcr: register is multicast/replicated in the
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* hardware and needs special handling. Any register
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* with this set should also use a type of xe_reg_mcr_t.
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* It's only here so the few places that deal with MCR
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* registers specially (xe_sr.c) and tests using the raw
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* value can inspect it.
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*/
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u32 mcr:1;
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/**
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* @vf: register is accessible from the Virtual Function.
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*/
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u32 vf:1;
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/**
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* @ext: access MMIO extension space for current register.
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*/
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u32 ext:1;
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};
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/** @raw: Raw value with both address and options */
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u32 raw;
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};
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};
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static_assert(sizeof(struct xe_reg) == sizeof(u32));
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/**
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* struct xe_reg_mcr - MCR register definition
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*
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* MCR register is the same as a regular register, but uses another type since
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* the internal API used for accessing them is different: it's never correct to
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* use regular MMIO access.
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*/
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struct xe_reg_mcr {
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/** @__reg: The register */
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struct xe_reg __reg;
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};
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/**
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* XE_REG_OPTION_MASKED - Register is "masked", with upper 16 bits marking the
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* written bits on the lower 16 bits.
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*
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* It only applies to registers explicitly marked in bspec with
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* "Access: Masked". Registers with this option can have write operations to
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* specific lower bits by setting the corresponding upper bits. Other bits will
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* not be affected. This allows register writes without needing a RMW cycle and
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* without caching in software the register value.
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*
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* Example: a write with value 0x00010001 will set bit 0 and all other bits
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* retain their previous values.
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*
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* To be used with XE_REG(). XE_REG_MCR() and XE_REG_INITIALIZER()
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*/
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#define XE_REG_OPTION_MASKED .masked = 1
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/**
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* XE_REG_OPTION_VF - Register is "VF" accessible.
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*
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* To be used with XE_REG() and XE_REG_INITIALIZER().
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*/
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#define XE_REG_OPTION_VF .vf = 1
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/**
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* XE_REG_INITIALIZER - Initializer for xe_reg_t.
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* @r_: Register offset
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* @...: Additional options like access mode. See struct xe_reg for available
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* options.
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*
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* Register field is mandatory, and additional options may be passed as
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* arguments. Usually ``XE_REG()`` should be preferred since it creates an
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* object of the right type. However when initializing static const storage,
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* where a compound statement is not allowed, this can be used instead.
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*/
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#define XE_REG_INITIALIZER(r_, ...) { .addr = r_, __VA_ARGS__ }
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/**
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* XE_REG - Create a struct xe_reg from offset and additional flags
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* @r_: Register offset
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* @...: Additional options like access mode. See struct xe_reg for available
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* options.
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*/
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#define XE_REG(r_, ...) ((const struct xe_reg)XE_REG_INITIALIZER(r_, ##__VA_ARGS__))
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/**
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* XE_REG_EXT - Create a struct xe_reg from extension offset and additional
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* flags
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* @r_: Register extension offset
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* @...: Additional options like access mode. See struct xe_reg for available
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* options.
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*/
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#define XE_REG_EXT(r_, ...) \
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((const struct xe_reg)XE_REG_INITIALIZER(r_, ##__VA_ARGS__, .ext = 1))
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/**
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* XE_REG_MCR - Create a struct xe_reg_mcr from offset and additional flags
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* @r_: Register offset
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* @...: Additional options like access mode. See struct xe_reg for available
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* options.
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*/
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#define XE_REG_MCR(r_, ...) ((const struct xe_reg_mcr){ \
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.__reg = XE_REG_INITIALIZER(r_, ##__VA_ARGS__, .mcr = 1) \
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})
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static inline bool xe_reg_is_valid(struct xe_reg r)
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{
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return r.addr;
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}
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#endif
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