37 lines
1.2 KiB
C
37 lines
1.2 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2023 Intel Corporation
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*/
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#ifndef _XE_GSC_COMMANDS_H_
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#define _XE_GSC_COMMANDS_H_
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#include "instructions/xe_instr_defs.h"
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/*
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* All GSCCS-specific commands have fixed length, so we can include it in the
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* defines. Note that the generic GSC command header structure includes an
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* optional data field in bits 9-21, but there are no commands that actually use
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* it; some of the commands are instead defined as having an extended length
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* field spanning bits 0-15, even if the extra bits are not required because the
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* longest GSCCS command is only 8 dwords. To handle this, the defines below use
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* a single field for both data and len. If we ever get a commands that does
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* actually have data and this approach doesn't work for it we can re-work it
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* at that point.
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*/
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#define GSC_OPCODE REG_GENMASK(28, 22)
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#define GSC_CMD_DATA_AND_LEN REG_GENMASK(21, 0)
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#define __GSC_INSTR(op, dl) \
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(XE_INSTR_GSC | \
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REG_FIELD_PREP(GSC_OPCODE, op) | \
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REG_FIELD_PREP(GSC_CMD_DATA_AND_LEN, dl))
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#define GSC_HECI_CMD_PKT __GSC_INSTR(0, 6)
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#define GSC_FW_LOAD __GSC_INSTR(1, 2)
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#define GSC_FW_LOAD_LIMIT_VALID REG_BIT(31)
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#endif
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