359 lines
14 KiB
C
359 lines
14 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2021 Intel Corporation
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*/
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#ifndef _ABI_GUC_KLVS_ABI_H
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#define _ABI_GUC_KLVS_ABI_H
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#include <linux/types.h>
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/**
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* DOC: GuC KLV
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*
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* +---+-------+--------------------------------------------------------------+
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* | | Bits | Description |
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* +===+=======+==============================================================+
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* | 0 | 31:16 | **KEY** - KLV key identifier |
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* | | | - `GuC Self Config KLVs`_ |
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* | | | - `GuC VGT Policy KLVs`_ |
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* | | | - `GuC VF Configuration KLVs`_ |
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* | | | |
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* | +-------+--------------------------------------------------------------+
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* | | 15:0 | **LEN** - length of VALUE (in 32bit dwords) |
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* +---+-------+--------------------------------------------------------------+
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* | 1 | 31:0 | **VALUE** - actual value of the KLV (format depends on KEY) |
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* +---+-------+ |
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* |...| | |
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* +---+-------+ |
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* | n | 31:0 | |
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* +---+-------+--------------------------------------------------------------+
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*/
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#define GUC_KLV_LEN_MIN 1u
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#define GUC_KLV_0_KEY (0xffffu << 16)
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#define GUC_KLV_0_LEN (0xffffu << 0)
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#define GUC_KLV_n_VALUE (0xffffffffu << 0)
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/**
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* DOC: GuC Global Config KLVs
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*
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* `GuC KLV`_ keys available for use with HOST2GUC_SELF_CFG_.
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*
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* _`GUC_KLV_GLOBAL_CFG_GMD_ID` : 0x3000
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* Refers to 32 bit architecture version as reported by the HW IP.
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* This key is supported on MTL+ platforms only.
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* Requires GuC ABI 1.2+.
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*/
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#define GUC_KLV_GLOBAL_CFG_GMD_ID_KEY 0x3000u
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#define GUC_KLV_GLOBAL_CFG_GMD_ID_LEN 1u
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/**
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* DOC: GuC Self Config KLVs
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*
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* `GuC KLV`_ keys available for use with HOST2GUC_SELF_CFG_.
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*
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* _`GUC_KLV_SELF_CFG_MEMIRQ_STATUS_ADDR` : 0x0900
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* Refers to 64 bit Global Gfx address (in bytes) of memory based interrupts
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* status vector for use by the GuC.
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*
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* _`GUC_KLV_SELF_CFG_MEMIRQ_SOURCE_ADDR` : 0x0901
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* Refers to 64 bit Global Gfx address (in bytes) of memory based interrupts
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* source vector for use by the GuC.
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*
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* _`GUC_KLV_SELF_CFG_H2G_CTB_ADDR` : 0x0902
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* Refers to 64 bit Global Gfx address of H2G `CT Buffer`_.
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* Should be above WOPCM address but below APIC base address for native mode.
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*
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* _`GUC_KLV_SELF_CFG_H2G_CTB_DESCRIPTOR_ADDR : 0x0903
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* Refers to 64 bit Global Gfx address of H2G `CTB Descriptor`_.
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* Should be above WOPCM address but below APIC base address for native mode.
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*
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* _`GUC_KLV_SELF_CFG_H2G_CTB_SIZE : 0x0904
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* Refers to size of H2G `CT Buffer`_ in bytes.
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* Should be a multiple of 4K.
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*
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* _`GUC_KLV_SELF_CFG_G2H_CTB_ADDR : 0x0905
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* Refers to 64 bit Global Gfx address of G2H `CT Buffer`_.
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* Should be above WOPCM address but below APIC base address for native mode.
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*
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* _GUC_KLV_SELF_CFG_G2H_CTB_DESCRIPTOR_ADDR : 0x0906
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* Refers to 64 bit Global Gfx address of G2H `CTB Descriptor`_.
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* Should be above WOPCM address but below APIC base address for native mode.
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*
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* _GUC_KLV_SELF_CFG_G2H_CTB_SIZE : 0x0907
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* Refers to size of G2H `CT Buffer`_ in bytes.
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* Should be a multiple of 4K.
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*/
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#define GUC_KLV_SELF_CFG_MEMIRQ_STATUS_ADDR_KEY 0x0900
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#define GUC_KLV_SELF_CFG_MEMIRQ_STATUS_ADDR_LEN 2u
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#define GUC_KLV_SELF_CFG_MEMIRQ_SOURCE_ADDR_KEY 0x0901
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#define GUC_KLV_SELF_CFG_MEMIRQ_SOURCE_ADDR_LEN 2u
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#define GUC_KLV_SELF_CFG_H2G_CTB_ADDR_KEY 0x0902
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#define GUC_KLV_SELF_CFG_H2G_CTB_ADDR_LEN 2u
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#define GUC_KLV_SELF_CFG_H2G_CTB_DESCRIPTOR_ADDR_KEY 0x0903
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#define GUC_KLV_SELF_CFG_H2G_CTB_DESCRIPTOR_ADDR_LEN 2u
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#define GUC_KLV_SELF_CFG_H2G_CTB_SIZE_KEY 0x0904
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#define GUC_KLV_SELF_CFG_H2G_CTB_SIZE_LEN 1u
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#define GUC_KLV_SELF_CFG_G2H_CTB_ADDR_KEY 0x0905
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#define GUC_KLV_SELF_CFG_G2H_CTB_ADDR_LEN 2u
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#define GUC_KLV_SELF_CFG_G2H_CTB_DESCRIPTOR_ADDR_KEY 0x0906
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#define GUC_KLV_SELF_CFG_G2H_CTB_DESCRIPTOR_ADDR_LEN 2u
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#define GUC_KLV_SELF_CFG_G2H_CTB_SIZE_KEY 0x0907
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#define GUC_KLV_SELF_CFG_G2H_CTB_SIZE_LEN 1u
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/*
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* Per context scheduling policy update keys.
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*/
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enum {
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GUC_CONTEXT_POLICIES_KLV_ID_EXECUTION_QUANTUM = 0x2001,
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GUC_CONTEXT_POLICIES_KLV_ID_PREEMPTION_TIMEOUT = 0x2002,
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GUC_CONTEXT_POLICIES_KLV_ID_SCHEDULING_PRIORITY = 0x2003,
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GUC_CONTEXT_POLICIES_KLV_ID_PREEMPT_TO_IDLE_ON_QUANTUM_EXPIRY = 0x2004,
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GUC_CONTEXT_POLICIES_KLV_ID_SLPM_GT_FREQUENCY = 0x2005,
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GUC_CONTEXT_POLICIES_KLV_NUM_IDS = 5,
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};
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/**
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* DOC: GuC VGT Policy KLVs
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*
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* `GuC KLV`_ keys available for use with PF2GUC_UPDATE_VGT_POLICY.
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*
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* _`GUC_KLV_VGT_POLICY_SCHED_IF_IDLE` : 0x8001
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* This config sets whether strict scheduling is enabled whereby any VF
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* that doesn’t have work to submit is still allocated a fixed execution
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* time-slice to ensure active VFs execution is always consitent even
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* during other VF reprovisiong / rebooting events. Changing this KLV
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* impacts all VFs and takes effect on the next VF-Switch event.
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*
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* :0: don't schedule idle (default)
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* :1: schedule if idle
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*
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* _`GUC_KLV_VGT_POLICY_ADVERSE_SAMPLE_PERIOD` : 0x8002
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* This config sets the sample period for tracking adverse event counters.
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* A sample period is the period in millisecs during which events are counted.
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* This is applicable for all the VFs.
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*
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* :0: adverse events are not counted (default)
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* :n: sample period in milliseconds
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*
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* _`GUC_KLV_VGT_POLICY_RESET_AFTER_VF_SWITCH` : 0x8D00
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* This enum is to reset utilized HW engine after VF Switch (i.e to clean
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* up Stale HW register left behind by previous VF)
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*
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* :0: don't reset (default)
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* :1: reset
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*/
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#define GUC_KLV_VGT_POLICY_SCHED_IF_IDLE_KEY 0x8001
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#define GUC_KLV_VGT_POLICY_SCHED_IF_IDLE_LEN 1u
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#define GUC_KLV_VGT_POLICY_ADVERSE_SAMPLE_PERIOD_KEY 0x8002
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#define GUC_KLV_VGT_POLICY_ADVERSE_SAMPLE_PERIOD_LEN 1u
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#define GUC_KLV_VGT_POLICY_RESET_AFTER_VF_SWITCH_KEY 0x8D00
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#define GUC_KLV_VGT_POLICY_RESET_AFTER_VF_SWITCH_LEN 1u
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/**
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* DOC: GuC VF Configuration KLVs
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*
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* `GuC KLV`_ keys available for use with PF2GUC_UPDATE_VF_CFG.
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*
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* _`GUC_KLV_VF_CFG_GGTT_START` : 0x0001
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* A 4K aligned start GTT address/offset assigned to VF.
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* Value is 64 bits.
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*
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* _`GUC_KLV_VF_CFG_GGTT_SIZE` : 0x0002
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* A 4K aligned size of GGTT assigned to VF.
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* Value is 64 bits.
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*
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* _`GUC_KLV_VF_CFG_LMEM_SIZE` : 0x0003
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* A 2M aligned size of local memory assigned to VF.
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* Value is 64 bits.
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*
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* _`GUC_KLV_VF_CFG_NUM_CONTEXTS` : 0x0004
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* Refers to the number of contexts allocated to this VF.
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*
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* :0: no contexts (default)
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* :1-65535: number of contexts (Gen12)
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*
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* _`GUC_KLV_VF_CFG_TILE_MASK` : 0x0005
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* For multi-tiled products, this field contains the bitwise-OR of tiles
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* assigned to the VF. Bit-0-set means VF has access to Tile-0,
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* Bit-31-set means VF has access to Tile-31, and etc.
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* At least one tile will always be allocated.
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* If all bits are zero, VF KMD should treat this as a fatal error.
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* For, single-tile products this KLV config is ignored.
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*
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* _`GUC_KLV_VF_CFG_NUM_DOORBELLS` : 0x0006
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* Refers to the number of doorbells allocated to this VF.
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*
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* :0: no doorbells (default)
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* :1-255: number of doorbells (Gen12)
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*
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* _`GUC_KLV_VF_CFG_EXEC_QUANTUM` : 0x8A01
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* This config sets the VFs-execution-quantum in milliseconds.
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* GUC will attempt to obey the maximum values as much as HW is capable
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* of and this will never be perfectly-exact (accumulated nano-second
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* granularity) since the GPUs clock time runs off a different crystal
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* from the CPUs clock. Changing this KLV on a VF that is currently
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* running a context wont take effect until a new context is scheduled in.
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* That said, when the PF is changing this value from 0x0 to
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* a non-zero value, it might never take effect if the VF is running an
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* infinitely long compute or shader kernel. In such a scenario, the
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* PF would need to trigger a VM PAUSE and then change the KLV to force
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* it to take effect. Such cases might typically happen on a 1PF+1VF
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* Virtualization config enabled for heavier workloads like AI/ML.
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*
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* The max value for this KLV is 100 seconds, anything exceeding that
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* will be clamped to the max.
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*
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* :0: infinite exec quantum (default)
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* :100000: maximum exec quantum (100000ms == 100s)
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*
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* _`GUC_KLV_VF_CFG_PREEMPT_TIMEOUT` : 0x8A02
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* This config sets the VF-preemption-timeout in microseconds.
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* GUC will attempt to obey the minimum and maximum values as much as
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* HW is capable and this will never be perfectly-exact (accumulated
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* nano-second granularity) since the GPUs clock time runs off a
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* different crystal from the CPUs clock. Changing this KLV on a VF
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* that is currently running a context wont take effect until a new
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* context is scheduled in.
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* That said, when the PF is changing this value from 0x0 to
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* a non-zero value, it might never take effect if the VF is running an
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* infinitely long compute or shader kernel.
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* In this case, the PF would need to trigger a VM PAUSE and then change
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* the KLV to force it to take effect. Such cases might typically happen
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* on a 1PF+1VF Virtualization config enabled for heavier workloads like
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* AI/ML.
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*
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* The max value for this KLV is 100 seconds, anything exceeding that
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* will be clamped to the max.
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*
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* :0: no preemption timeout (default)
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* :100000000: maximum preemption timeout (100000000us == 100s)
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*
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* _`GUC_KLV_VF_CFG_THRESHOLD_CAT_ERR` : 0x8A03
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* This config sets threshold for CAT errors caused by the VF.
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*
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* :0: adverse events or error will not be reported (default)
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* :n: event occurrence count per sampling interval
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*
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* _`GUC_KLV_VF_CFG_THRESHOLD_ENGINE_RESET` : 0x8A04
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* This config sets threshold for engine reset caused by the VF.
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*
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* :0: adverse events or error will not be reported (default)
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* :n: event occurrence count per sampling interval
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*
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* _`GUC_KLV_VF_CFG_THRESHOLD_PAGE_FAULT` : 0x8A05
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* This config sets threshold for page fault errors caused by the VF.
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*
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* :0: adverse events or error will not be reported (default)
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* :n: event occurrence count per sampling interval
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*
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* _`GUC_KLV_VF_CFG_THRESHOLD_H2G_STORM` : 0x8A06
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* This config sets threshold for H2G interrupts triggered by the VF.
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*
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* :0: adverse events or error will not be reported (default)
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* :n: time (us) per sampling interval
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*
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* _`GUC_KLV_VF_CFG_THRESHOLD_IRQ_STORM` : 0x8A07
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* This config sets threshold for GT interrupts triggered by the VF's
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* workloads.
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*
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* :0: adverse events or error will not be reported (default)
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* :n: time (us) per sampling interval
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*
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* _`GUC_KLV_VF_CFG_THRESHOLD_DOORBELL_STORM` : 0x8A08
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* This config sets threshold for doorbell's ring triggered by the VF.
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*
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* :0: adverse events or error will not be reported (default)
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* :n: time (us) per sampling interval
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*
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* _`GUC_KLV_VF_CFG_BEGIN_DOORBELL_ID` : 0x8A0A
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* Refers to the start index of doorbell assigned to this VF.
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*
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* :0: (default)
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* :1-255: number of doorbells (Gen12)
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*
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* _`GUC_KLV_VF_CFG_BEGIN_CONTEXT_ID` : 0x8A0B
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* Refers to the start index in context array allocated to this VF’s use.
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*
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* :0: (default)
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* :1-65535: number of contexts (Gen12)
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*/
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#define GUC_KLV_VF_CFG_GGTT_START_KEY 0x0001
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#define GUC_KLV_VF_CFG_GGTT_START_LEN 2u
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#define GUC_KLV_VF_CFG_GGTT_SIZE_KEY 0x0002
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#define GUC_KLV_VF_CFG_GGTT_SIZE_LEN 2u
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#define GUC_KLV_VF_CFG_LMEM_SIZE_KEY 0x0003
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#define GUC_KLV_VF_CFG_LMEM_SIZE_LEN 2u
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#define GUC_KLV_VF_CFG_NUM_CONTEXTS_KEY 0x0004
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#define GUC_KLV_VF_CFG_NUM_CONTEXTS_LEN 1u
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#define GUC_KLV_VF_CFG_TILE_MASK_KEY 0x0005
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#define GUC_KLV_VF_CFG_TILE_MASK_LEN 1u
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#define GUC_KLV_VF_CFG_NUM_DOORBELLS_KEY 0x0006
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#define GUC_KLV_VF_CFG_NUM_DOORBELLS_LEN 1u
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#define GUC_KLV_VF_CFG_EXEC_QUANTUM_KEY 0x8a01
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#define GUC_KLV_VF_CFG_EXEC_QUANTUM_LEN 1u
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#define GUC_KLV_VF_CFG_EXEC_QUANTUM_MAX_VALUE 100000u
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#define GUC_KLV_VF_CFG_PREEMPT_TIMEOUT_KEY 0x8a02
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#define GUC_KLV_VF_CFG_PREEMPT_TIMEOUT_LEN 1u
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#define GUC_KLV_VF_CFG_PREEMPT_TIMEOUT_MAX_VALUE 100000000u
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#define GUC_KLV_VF_CFG_THRESHOLD_CAT_ERR_KEY 0x8a03
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#define GUC_KLV_VF_CFG_THRESHOLD_CAT_ERR_LEN 1u
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#define GUC_KLV_VF_CFG_THRESHOLD_ENGINE_RESET_KEY 0x8a04
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#define GUC_KLV_VF_CFG_THRESHOLD_ENGINE_RESET_LEN 1u
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#define GUC_KLV_VF_CFG_THRESHOLD_PAGE_FAULT_KEY 0x8a05
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#define GUC_KLV_VF_CFG_THRESHOLD_PAGE_FAULT_LEN 1u
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#define GUC_KLV_VF_CFG_THRESHOLD_H2G_STORM_KEY 0x8a06
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#define GUC_KLV_VF_CFG_THRESHOLD_H2G_STORM_LEN 1u
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#define GUC_KLV_VF_CFG_THRESHOLD_IRQ_STORM_KEY 0x8a07
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#define GUC_KLV_VF_CFG_THRESHOLD_IRQ_STORM_LEN 1u
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#define GUC_KLV_VF_CFG_THRESHOLD_DOORBELL_STORM_KEY 0x8a08
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#define GUC_KLV_VF_CFG_THRESHOLD_DOORBELL_STORM_LEN 1u
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#define GUC_KLV_VF_CFG_BEGIN_DOORBELL_ID_KEY 0x8a0a
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#define GUC_KLV_VF_CFG_BEGIN_DOORBELL_ID_LEN 1u
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#define GUC_KLV_VF_CFG_BEGIN_CONTEXT_ID_KEY 0x8a0b
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#define GUC_KLV_VF_CFG_BEGIN_CONTEXT_ID_LEN 1u
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/*
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* Workaround keys:
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*/
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enum xe_guc_klv_ids {
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GUC_WORKAROUND_KLV_BLOCK_INTERRUPTS_WHEN_MGSR_BLOCKED = 0x9002,
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GUC_WORKAROUND_KLV_ID_GAM_PFQ_SHADOW_TAIL_POLLING = 0x9005,
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GUC_WORKAROUND_KLV_ID_DISABLE_MTP_DURING_ASYNC_COMPUTE = 0x9007,
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GUC_WA_KLV_NP_RD_WRITE_TO_CLEAR_RCSM_AT_CGP_LATE_RESTORE = 0x9008,
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GUC_WORKAROUND_KLV_ID_BACK_TO_BACK_RCS_ENGINE_RESET = 0x9009,
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GUC_WA_KLV_WAKE_POWER_DOMAINS_FOR_OUTBOUND_MMIO = 0x900a,
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};
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#endif
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