425 lines
12 KiB
C
425 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (c) 2021-2022 Rockchip Electronics Co., Ltd.
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* Copyright (c) 2024 Collabora Ltd.
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*
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* Author: Algea Cao <algea.cao@rock-chips.com>
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* Author: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
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*/
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#include <linux/clk.h>
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#include <linux/gpio/consumer.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/phy/phy.h>
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#include <linux/regmap.h>
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#include <linux/workqueue.h>
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#include <drm/bridge/dw_hdmi_qp.h>
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#include <drm/display/drm_hdmi_helper.h>
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#include <drm/drm_bridge_connector.h>
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#include <drm/drm_of.h>
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#include <drm/drm_probe_helper.h>
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#include <drm/drm_simple_kms_helper.h>
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#include "rockchip_drm_drv.h"
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#define RK3588_GRF_SOC_CON2 0x0308
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#define RK3588_HDMI0_HPD_INT_MSK BIT(13)
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#define RK3588_HDMI0_HPD_INT_CLR BIT(12)
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#define RK3588_GRF_SOC_CON7 0x031c
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#define RK3588_SET_HPD_PATH_MASK GENMASK(13, 12)
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#define RK3588_GRF_SOC_STATUS1 0x0384
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#define RK3588_HDMI0_LEVEL_INT BIT(16)
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#define RK3588_GRF_VO1_CON3 0x000c
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#define RK3588_SCLIN_MASK BIT(9)
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#define RK3588_SDAIN_MASK BIT(10)
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#define RK3588_MODE_MASK BIT(11)
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#define RK3588_I2S_SEL_MASK BIT(13)
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#define RK3588_GRF_VO1_CON9 0x0024
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#define RK3588_HDMI0_GRANT_SEL BIT(10)
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#define HIWORD_UPDATE(val, mask) ((val) | (mask) << 16)
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#define HOTPLUG_DEBOUNCE_MS 150
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struct rockchip_hdmi_qp {
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struct device *dev;
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struct regmap *regmap;
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struct regmap *vo_regmap;
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struct rockchip_encoder encoder;
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struct clk *ref_clk;
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struct dw_hdmi_qp *hdmi;
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struct phy *phy;
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struct gpio_desc *enable_gpio;
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struct delayed_work hpd_work;
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};
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static struct rockchip_hdmi_qp *to_rockchip_hdmi_qp(struct drm_encoder *encoder)
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{
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struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder);
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return container_of(rkencoder, struct rockchip_hdmi_qp, encoder);
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}
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static void dw_hdmi_qp_rockchip_encoder_enable(struct drm_encoder *encoder)
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{
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struct rockchip_hdmi_qp *hdmi = to_rockchip_hdmi_qp(encoder);
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struct drm_crtc *crtc = encoder->crtc;
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unsigned long long rate;
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/* Unconditionally switch to TMDS as FRL is not yet supported */
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gpiod_set_value(hdmi->enable_gpio, 1);
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if (crtc && crtc->state) {
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rate = drm_hdmi_compute_mode_clock(&crtc->state->adjusted_mode,
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8, HDMI_COLORSPACE_RGB);
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clk_set_rate(hdmi->ref_clk, rate);
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/*
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* FIXME: Temporary workaround to pass pixel clock rate
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* to the PHY driver until phy_configure_opts_hdmi
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* becomes available in the PHY API. See also the related
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* comment in rk_hdptx_phy_power_on() from
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* drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
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*/
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phy_set_bus_width(hdmi->phy, div_u64(rate, 100));
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}
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}
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static int
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dw_hdmi_qp_rockchip_encoder_atomic_check(struct drm_encoder *encoder,
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struct drm_crtc_state *crtc_state,
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struct drm_connector_state *conn_state)
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{
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struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
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s->output_mode = ROCKCHIP_OUT_MODE_AAAA;
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s->output_type = DRM_MODE_CONNECTOR_HDMIA;
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return 0;
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}
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static const struct
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drm_encoder_helper_funcs dw_hdmi_qp_rockchip_encoder_helper_funcs = {
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.enable = dw_hdmi_qp_rockchip_encoder_enable,
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.atomic_check = dw_hdmi_qp_rockchip_encoder_atomic_check,
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};
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static int dw_hdmi_qp_rk3588_phy_init(struct dw_hdmi_qp *dw_hdmi, void *data)
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{
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struct rockchip_hdmi_qp *hdmi = (struct rockchip_hdmi_qp *)data;
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return phy_power_on(hdmi->phy);
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}
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static void dw_hdmi_qp_rk3588_phy_disable(struct dw_hdmi_qp *dw_hdmi,
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void *data)
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{
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struct rockchip_hdmi_qp *hdmi = (struct rockchip_hdmi_qp *)data;
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phy_power_off(hdmi->phy);
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}
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static enum drm_connector_status
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dw_hdmi_qp_rk3588_read_hpd(struct dw_hdmi_qp *dw_hdmi, void *data)
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{
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struct rockchip_hdmi_qp *hdmi = (struct rockchip_hdmi_qp *)data;
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u32 val;
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regmap_read(hdmi->regmap, RK3588_GRF_SOC_STATUS1, &val);
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return val & RK3588_HDMI0_LEVEL_INT ?
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connector_status_connected : connector_status_disconnected;
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}
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static void dw_hdmi_qp_rk3588_setup_hpd(struct dw_hdmi_qp *dw_hdmi, void *data)
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{
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struct rockchip_hdmi_qp *hdmi = (struct rockchip_hdmi_qp *)data;
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regmap_write(hdmi->regmap,
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RK3588_GRF_SOC_CON2,
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HIWORD_UPDATE(RK3588_HDMI0_HPD_INT_CLR,
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RK3588_HDMI0_HPD_INT_CLR |
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RK3588_HDMI0_HPD_INT_MSK));
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}
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static const struct dw_hdmi_qp_phy_ops rk3588_hdmi_phy_ops = {
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.init = dw_hdmi_qp_rk3588_phy_init,
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.disable = dw_hdmi_qp_rk3588_phy_disable,
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.read_hpd = dw_hdmi_qp_rk3588_read_hpd,
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.setup_hpd = dw_hdmi_qp_rk3588_setup_hpd,
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};
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static void dw_hdmi_qp_rk3588_hpd_work(struct work_struct *work)
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{
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struct rockchip_hdmi_qp *hdmi = container_of(work,
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struct rockchip_hdmi_qp,
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hpd_work.work);
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struct drm_device *drm = hdmi->encoder.encoder.dev;
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bool changed;
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if (drm) {
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changed = drm_helper_hpd_irq_event(drm);
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if (changed)
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drm_dbg(hdmi, "connector status changed\n");
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}
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}
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static irqreturn_t dw_hdmi_qp_rk3588_hardirq(int irq, void *dev_id)
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{
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struct rockchip_hdmi_qp *hdmi = dev_id;
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u32 intr_stat, val;
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regmap_read(hdmi->regmap, RK3588_GRF_SOC_STATUS1, &intr_stat);
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if (intr_stat) {
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val = HIWORD_UPDATE(RK3588_HDMI0_HPD_INT_MSK,
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RK3588_HDMI0_HPD_INT_MSK);
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regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val);
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return IRQ_WAKE_THREAD;
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}
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return IRQ_NONE;
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}
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static irqreturn_t dw_hdmi_qp_rk3588_irq(int irq, void *dev_id)
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{
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struct rockchip_hdmi_qp *hdmi = dev_id;
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u32 intr_stat, val;
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regmap_read(hdmi->regmap, RK3588_GRF_SOC_STATUS1, &intr_stat);
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if (!intr_stat)
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return IRQ_NONE;
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val = HIWORD_UPDATE(RK3588_HDMI0_HPD_INT_CLR,
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RK3588_HDMI0_HPD_INT_CLR);
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regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val);
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mod_delayed_work(system_wq, &hdmi->hpd_work,
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msecs_to_jiffies(HOTPLUG_DEBOUNCE_MS));
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val |= HIWORD_UPDATE(0, RK3588_HDMI0_HPD_INT_MSK);
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regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val);
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return IRQ_HANDLED;
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}
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static const struct of_device_id dw_hdmi_qp_rockchip_dt_ids[] = {
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{ .compatible = "rockchip,rk3588-dw-hdmi-qp",
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.data = &rk3588_hdmi_phy_ops },
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{},
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};
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MODULE_DEVICE_TABLE(of, dw_hdmi_qp_rockchip_dt_ids);
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static int dw_hdmi_qp_rockchip_bind(struct device *dev, struct device *master,
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void *data)
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{
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static const char * const clk_names[] = {
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"pclk", "earc", "aud", "hdp", "hclk_vo1",
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"ref" /* keep "ref" last */
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};
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struct platform_device *pdev = to_platform_device(dev);
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struct dw_hdmi_qp_plat_data plat_data;
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struct drm_device *drm = data;
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struct drm_connector *connector;
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struct drm_encoder *encoder;
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struct rockchip_hdmi_qp *hdmi;
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struct clk *clk;
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int ret, irq, i;
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u32 val;
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if (!pdev->dev.of_node)
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return -ENODEV;
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hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
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if (!hdmi)
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return -ENOMEM;
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plat_data.phy_ops = of_device_get_match_data(dev);
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if (!plat_data.phy_ops)
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return -ENODEV;
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plat_data.phy_data = hdmi;
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hdmi->dev = &pdev->dev;
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encoder = &hdmi->encoder.encoder;
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encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
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rockchip_drm_encoder_set_crtc_endpoint_id(&hdmi->encoder,
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dev->of_node, 0, 0);
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/*
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* If we failed to find the CRTC(s) which this encoder is
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* supposed to be connected to, it's because the CRTC has
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* not been registered yet. Defer probing, and hope that
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* the required CRTC is added later.
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*/
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if (encoder->possible_crtcs == 0)
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return -EPROBE_DEFER;
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hdmi->regmap = syscon_regmap_lookup_by_phandle(dev->of_node,
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"rockchip,grf");
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if (IS_ERR(hdmi->regmap)) {
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drm_err(hdmi, "Unable to get rockchip,grf\n");
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return PTR_ERR(hdmi->regmap);
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}
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hdmi->vo_regmap = syscon_regmap_lookup_by_phandle(dev->of_node,
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"rockchip,vo-grf");
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if (IS_ERR(hdmi->vo_regmap)) {
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drm_err(hdmi, "Unable to get rockchip,vo-grf\n");
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return PTR_ERR(hdmi->vo_regmap);
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}
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for (i = 0; i < ARRAY_SIZE(clk_names); i++) {
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clk = devm_clk_get_enabled(hdmi->dev, clk_names[i]);
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if (IS_ERR(clk)) {
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ret = PTR_ERR(clk);
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if (ret != -EPROBE_DEFER)
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drm_err(hdmi, "Failed to get %s clock: %d\n",
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clk_names[i], ret);
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return ret;
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}
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}
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hdmi->ref_clk = clk;
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hdmi->enable_gpio = devm_gpiod_get_optional(hdmi->dev, "enable",
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GPIOD_OUT_HIGH);
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if (IS_ERR(hdmi->enable_gpio)) {
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ret = PTR_ERR(hdmi->enable_gpio);
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drm_err(hdmi, "Failed to request enable GPIO: %d\n", ret);
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return ret;
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}
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hdmi->phy = devm_of_phy_get_by_index(dev, dev->of_node, 0);
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if (IS_ERR(hdmi->phy)) {
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ret = PTR_ERR(hdmi->phy);
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if (ret != -EPROBE_DEFER)
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drm_err(hdmi, "failed to get phy: %d\n", ret);
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return ret;
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}
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val = HIWORD_UPDATE(RK3588_SCLIN_MASK, RK3588_SCLIN_MASK) |
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HIWORD_UPDATE(RK3588_SDAIN_MASK, RK3588_SDAIN_MASK) |
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HIWORD_UPDATE(RK3588_MODE_MASK, RK3588_MODE_MASK) |
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HIWORD_UPDATE(RK3588_I2S_SEL_MASK, RK3588_I2S_SEL_MASK);
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regmap_write(hdmi->vo_regmap, RK3588_GRF_VO1_CON3, val);
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val = HIWORD_UPDATE(RK3588_SET_HPD_PATH_MASK,
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RK3588_SET_HPD_PATH_MASK);
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regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON7, val);
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val = HIWORD_UPDATE(RK3588_HDMI0_GRANT_SEL,
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RK3588_HDMI0_GRANT_SEL);
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regmap_write(hdmi->vo_regmap, RK3588_GRF_VO1_CON9, val);
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val = HIWORD_UPDATE(RK3588_HDMI0_HPD_INT_MSK, RK3588_HDMI0_HPD_INT_MSK);
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regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val);
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INIT_DELAYED_WORK(&hdmi->hpd_work, dw_hdmi_qp_rk3588_hpd_work);
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plat_data.main_irq = platform_get_irq_byname(pdev, "main");
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if (plat_data.main_irq < 0)
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return plat_data.main_irq;
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irq = platform_get_irq_byname(pdev, "hpd");
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if (irq < 0)
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return irq;
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ret = devm_request_threaded_irq(hdmi->dev, irq,
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dw_hdmi_qp_rk3588_hardirq,
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dw_hdmi_qp_rk3588_irq,
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IRQF_SHARED, "dw-hdmi-qp-hpd",
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hdmi);
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if (ret)
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return ret;
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drm_encoder_helper_add(encoder, &dw_hdmi_qp_rockchip_encoder_helper_funcs);
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drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
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platform_set_drvdata(pdev, hdmi);
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hdmi->hdmi = dw_hdmi_qp_bind(pdev, encoder, &plat_data);
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if (IS_ERR(hdmi->hdmi)) {
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ret = PTR_ERR(hdmi->hdmi);
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drm_encoder_cleanup(encoder);
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return ret;
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}
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connector = drm_bridge_connector_init(drm, encoder);
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if (IS_ERR(connector)) {
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ret = PTR_ERR(connector);
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drm_err(hdmi, "failed to init bridge connector: %d\n", ret);
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return ret;
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}
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return drm_connector_attach_encoder(connector, encoder);
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}
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static void dw_hdmi_qp_rockchip_unbind(struct device *dev,
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struct device *master,
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void *data)
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{
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struct rockchip_hdmi_qp *hdmi = dev_get_drvdata(dev);
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cancel_delayed_work_sync(&hdmi->hpd_work);
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drm_encoder_cleanup(&hdmi->encoder.encoder);
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}
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static const struct component_ops dw_hdmi_qp_rockchip_ops = {
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.bind = dw_hdmi_qp_rockchip_bind,
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.unbind = dw_hdmi_qp_rockchip_unbind,
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};
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static int dw_hdmi_qp_rockchip_probe(struct platform_device *pdev)
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{
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return component_add(&pdev->dev, &dw_hdmi_qp_rockchip_ops);
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}
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static void dw_hdmi_qp_rockchip_remove(struct platform_device *pdev)
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{
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component_del(&pdev->dev, &dw_hdmi_qp_rockchip_ops);
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}
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static int __maybe_unused dw_hdmi_qp_rockchip_resume(struct device *dev)
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{
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struct rockchip_hdmi_qp *hdmi = dev_get_drvdata(dev);
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u32 val;
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val = HIWORD_UPDATE(RK3588_SCLIN_MASK, RK3588_SCLIN_MASK) |
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HIWORD_UPDATE(RK3588_SDAIN_MASK, RK3588_SDAIN_MASK) |
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HIWORD_UPDATE(RK3588_MODE_MASK, RK3588_MODE_MASK) |
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HIWORD_UPDATE(RK3588_I2S_SEL_MASK, RK3588_I2S_SEL_MASK);
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regmap_write(hdmi->vo_regmap, RK3588_GRF_VO1_CON3, val);
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val = HIWORD_UPDATE(RK3588_SET_HPD_PATH_MASK,
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RK3588_SET_HPD_PATH_MASK);
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regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON7, val);
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val = HIWORD_UPDATE(RK3588_HDMI0_GRANT_SEL,
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RK3588_HDMI0_GRANT_SEL);
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regmap_write(hdmi->vo_regmap, RK3588_GRF_VO1_CON9, val);
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dw_hdmi_qp_resume(dev, hdmi->hdmi);
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if (hdmi->encoder.encoder.dev)
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drm_helper_hpd_irq_event(hdmi->encoder.encoder.dev);
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return 0;
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}
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static const struct dev_pm_ops dw_hdmi_qp_rockchip_pm = {
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SET_SYSTEM_SLEEP_PM_OPS(NULL, dw_hdmi_qp_rockchip_resume)
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};
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struct platform_driver dw_hdmi_qp_rockchip_pltfm_driver = {
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.probe = dw_hdmi_qp_rockchip_probe,
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.remove = dw_hdmi_qp_rockchip_remove,
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.driver = {
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.name = "dwhdmiqp-rockchip",
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.pm = &dw_hdmi_qp_rockchip_pm,
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.of_match_table = dw_hdmi_qp_rockchip_dt_ids,
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},
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};
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