504 lines
14 KiB
C
504 lines
14 KiB
C
/* SPDX-License-Identifier: GPL-2.0 or MIT */
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/* Copyright 2023 Collabora ltd. */
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#ifndef __PANTHOR_MCU_H__
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#define __PANTHOR_MCU_H__
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#include <linux/types.h>
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struct panthor_device;
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struct panthor_kernel_bo;
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#define MAX_CSGS 31
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#define MAX_CS_PER_CSG 32
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struct panthor_fw_ringbuf_input_iface {
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u64 insert;
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u64 extract;
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};
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struct panthor_fw_ringbuf_output_iface {
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u64 extract;
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u32 active;
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};
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struct panthor_fw_cs_control_iface {
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#define CS_FEATURES_WORK_REGS(x) (((x) & GENMASK(7, 0)) + 1)
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#define CS_FEATURES_SCOREBOARDS(x) (((x) & GENMASK(15, 8)) >> 8)
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#define CS_FEATURES_COMPUTE BIT(16)
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#define CS_FEATURES_FRAGMENT BIT(17)
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#define CS_FEATURES_TILER BIT(18)
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u32 features;
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u32 input_va;
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u32 output_va;
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};
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struct panthor_fw_cs_input_iface {
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#define CS_STATE_MASK GENMASK(2, 0)
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#define CS_STATE_STOP 0
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#define CS_STATE_START 1
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#define CS_EXTRACT_EVENT BIT(4)
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#define CS_IDLE_SYNC_WAIT BIT(8)
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#define CS_IDLE_PROTM_PENDING BIT(9)
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#define CS_IDLE_EMPTY BIT(10)
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#define CS_IDLE_RESOURCE_REQ BIT(11)
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#define CS_TILER_OOM BIT(26)
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#define CS_PROTM_PENDING BIT(27)
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#define CS_FATAL BIT(30)
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#define CS_FAULT BIT(31)
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#define CS_REQ_MASK (CS_STATE_MASK | \
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CS_EXTRACT_EVENT | \
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CS_IDLE_SYNC_WAIT | \
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CS_IDLE_PROTM_PENDING | \
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CS_IDLE_EMPTY | \
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CS_IDLE_RESOURCE_REQ)
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#define CS_EVT_MASK (CS_TILER_OOM | \
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CS_PROTM_PENDING | \
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CS_FATAL | \
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CS_FAULT)
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u32 req;
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#define CS_CONFIG_PRIORITY(x) ((x) & GENMASK(3, 0))
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#define CS_CONFIG_DOORBELL(x) (((x) << 8) & GENMASK(15, 8))
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u32 config;
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u32 reserved1;
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u32 ack_irq_mask;
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u64 ringbuf_base;
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u32 ringbuf_size;
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u32 reserved2;
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u64 heap_start;
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u64 heap_end;
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u64 ringbuf_input;
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u64 ringbuf_output;
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u32 instr_config;
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u32 instrbuf_size;
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u64 instrbuf_base;
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u64 instrbuf_offset_ptr;
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};
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struct panthor_fw_cs_output_iface {
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u32 ack;
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u32 reserved1[15];
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u64 status_cmd_ptr;
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#define CS_STATUS_WAIT_SB_MASK GENMASK(15, 0)
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#define CS_STATUS_WAIT_SB_SRC_MASK GENMASK(19, 16)
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#define CS_STATUS_WAIT_SB_SRC_NONE (0 << 16)
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#define CS_STATUS_WAIT_SB_SRC_WAIT (8 << 16)
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#define CS_STATUS_WAIT_SYNC_COND_LE (0 << 24)
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#define CS_STATUS_WAIT_SYNC_COND_GT (1 << 24)
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#define CS_STATUS_WAIT_SYNC_COND_MASK GENMASK(27, 24)
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#define CS_STATUS_WAIT_PROGRESS BIT(28)
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#define CS_STATUS_WAIT_PROTM BIT(29)
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#define CS_STATUS_WAIT_SYNC_64B BIT(30)
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#define CS_STATUS_WAIT_SYNC BIT(31)
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u32 status_wait;
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u32 status_req_resource;
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u64 status_wait_sync_ptr;
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u32 status_wait_sync_value;
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u32 status_scoreboards;
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#define CS_STATUS_BLOCKED_REASON_UNBLOCKED 0
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#define CS_STATUS_BLOCKED_REASON_SB_WAIT 1
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#define CS_STATUS_BLOCKED_REASON_PROGRESS_WAIT 2
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#define CS_STATUS_BLOCKED_REASON_SYNC_WAIT 3
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#define CS_STATUS_BLOCKED_REASON_DEFERRED 5
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#define CS_STATUS_BLOCKED_REASON_RES 6
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#define CS_STATUS_BLOCKED_REASON_FLUSH 7
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#define CS_STATUS_BLOCKED_REASON_MASK GENMASK(3, 0)
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u32 status_blocked_reason;
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u32 status_wait_sync_value_hi;
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u32 reserved2[6];
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#define CS_EXCEPTION_TYPE(x) ((x) & GENMASK(7, 0))
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#define CS_EXCEPTION_DATA(x) (((x) >> 8) & GENMASK(23, 0))
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u32 fault;
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u32 fatal;
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u64 fault_info;
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u64 fatal_info;
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u32 reserved3[10];
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u32 heap_vt_start;
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u32 heap_vt_end;
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u32 reserved4;
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u32 heap_frag_end;
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u64 heap_address;
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};
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struct panthor_fw_csg_control_iface {
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u32 features;
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u32 input_va;
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u32 output_va;
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u32 suspend_size;
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u32 protm_suspend_size;
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u32 stream_num;
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u32 stream_stride;
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};
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struct panthor_fw_csg_input_iface {
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#define CSG_STATE_MASK GENMASK(2, 0)
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#define CSG_STATE_TERMINATE 0
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#define CSG_STATE_START 1
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#define CSG_STATE_SUSPEND 2
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#define CSG_STATE_RESUME 3
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#define CSG_ENDPOINT_CONFIG BIT(4)
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#define CSG_STATUS_UPDATE BIT(5)
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#define CSG_SYNC_UPDATE BIT(28)
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#define CSG_IDLE BIT(29)
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#define CSG_DOORBELL BIT(30)
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#define CSG_PROGRESS_TIMER_EVENT BIT(31)
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#define CSG_REQ_MASK (CSG_STATE_MASK | \
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CSG_ENDPOINT_CONFIG | \
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CSG_STATUS_UPDATE)
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#define CSG_EVT_MASK (CSG_SYNC_UPDATE | \
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CSG_IDLE | \
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CSG_PROGRESS_TIMER_EVENT)
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u32 req;
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u32 ack_irq_mask;
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u32 doorbell_req;
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u32 cs_irq_ack;
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u32 reserved1[4];
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u64 allow_compute;
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u64 allow_fragment;
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u32 allow_other;
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#define CSG_EP_REQ_COMPUTE(x) ((x) & GENMASK(7, 0))
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#define CSG_EP_REQ_FRAGMENT(x) (((x) << 8) & GENMASK(15, 8))
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#define CSG_EP_REQ_TILER(x) (((x) << 16) & GENMASK(19, 16))
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#define CSG_EP_REQ_EXCL_COMPUTE BIT(20)
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#define CSG_EP_REQ_EXCL_FRAGMENT BIT(21)
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#define CSG_EP_REQ_PRIORITY(x) (((x) << 28) & GENMASK(31, 28))
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#define CSG_EP_REQ_PRIORITY_MASK GENMASK(31, 28)
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u32 endpoint_req;
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u32 reserved2[2];
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u64 suspend_buf;
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u64 protm_suspend_buf;
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u32 config;
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u32 iter_trace_config;
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};
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struct panthor_fw_csg_output_iface {
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u32 ack;
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u32 reserved1;
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u32 doorbell_ack;
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u32 cs_irq_req;
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u32 status_endpoint_current;
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u32 status_endpoint_req;
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#define CSG_STATUS_STATE_IS_IDLE BIT(0)
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u32 status_state;
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u32 resource_dep;
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};
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struct panthor_fw_global_control_iface {
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u32 version;
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u32 features;
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u32 input_va;
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u32 output_va;
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u32 group_num;
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u32 group_stride;
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u32 perfcnt_size;
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u32 instr_features;
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};
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struct panthor_fw_global_input_iface {
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#define GLB_HALT BIT(0)
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#define GLB_CFG_PROGRESS_TIMER BIT(1)
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#define GLB_CFG_ALLOC_EN BIT(2)
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#define GLB_CFG_POWEROFF_TIMER BIT(3)
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#define GLB_PROTM_ENTER BIT(4)
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#define GLB_PERFCNT_EN BIT(5)
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#define GLB_PERFCNT_SAMPLE BIT(6)
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#define GLB_COUNTER_EN BIT(7)
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#define GLB_PING BIT(8)
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#define GLB_FWCFG_UPDATE BIT(9)
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#define GLB_IDLE_EN BIT(10)
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#define GLB_SLEEP BIT(12)
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#define GLB_INACTIVE_COMPUTE BIT(20)
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#define GLB_INACTIVE_FRAGMENT BIT(21)
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#define GLB_INACTIVE_TILER BIT(22)
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#define GLB_PROTM_EXIT BIT(23)
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#define GLB_PERFCNT_THRESHOLD BIT(24)
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#define GLB_PERFCNT_OVERFLOW BIT(25)
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#define GLB_IDLE BIT(26)
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#define GLB_DBG_CSF BIT(30)
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#define GLB_DBG_HOST BIT(31)
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#define GLB_REQ_MASK GENMASK(10, 0)
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#define GLB_EVT_MASK GENMASK(26, 20)
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u32 req;
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u32 ack_irq_mask;
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u32 doorbell_req;
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u32 reserved1;
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u32 progress_timer;
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#define GLB_TIMER_VAL(x) ((x) & GENMASK(30, 0))
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#define GLB_TIMER_SOURCE_GPU_COUNTER BIT(31)
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u32 poweroff_timer;
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u64 core_en_mask;
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u32 reserved2;
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u32 perfcnt_as;
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u64 perfcnt_base;
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u32 perfcnt_extract;
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u32 reserved3[3];
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u32 perfcnt_config;
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u32 perfcnt_csg_select;
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u32 perfcnt_fw_enable;
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u32 perfcnt_csg_enable;
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u32 perfcnt_csf_enable;
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u32 perfcnt_shader_enable;
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u32 perfcnt_tiler_enable;
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u32 perfcnt_mmu_l2_enable;
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u32 reserved4[8];
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u32 idle_timer;
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};
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enum panthor_fw_halt_status {
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PANTHOR_FW_HALT_OK = 0,
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PANTHOR_FW_HALT_ON_PANIC = 0x4e,
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PANTHOR_FW_HALT_ON_WATCHDOG_EXPIRATION = 0x4f,
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};
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struct panthor_fw_global_output_iface {
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u32 ack;
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u32 reserved1;
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u32 doorbell_ack;
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u32 reserved2;
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u32 halt_status;
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u32 perfcnt_status;
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u32 perfcnt_insert;
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};
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/**
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* struct panthor_fw_cs_iface - Firmware command stream slot interface
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*/
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struct panthor_fw_cs_iface {
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/**
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* @lock: Lock protecting access to the panthor_fw_cs_input_iface::req
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* field.
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*
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* Needed so we can update the req field concurrently from the interrupt
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* handler and the scheduler logic.
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*
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* TODO: Ideally we'd want to use a cmpxchg() to update the req, but FW
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* interface sections are mapped uncached/write-combined right now, and
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* using cmpxchg() on such mappings leads to SError faults. Revisit when
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* we have 'SHARED' GPU mappings hooked up.
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*/
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spinlock_t lock;
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/**
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* @control: Command stream slot control interface.
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*
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* Used to expose command stream slot properties.
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*
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* This interface is read-only.
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*/
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struct panthor_fw_cs_control_iface *control;
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/**
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* @input: Command stream slot input interface.
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*
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* Used for host updates/events.
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*/
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struct panthor_fw_cs_input_iface *input;
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/**
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* @output: Command stream slot output interface.
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*
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* Used for FW updates/events.
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*
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* This interface is read-only.
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*/
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const struct panthor_fw_cs_output_iface *output;
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};
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/**
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* struct panthor_fw_csg_iface - Firmware command stream group slot interface
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*/
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struct panthor_fw_csg_iface {
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/**
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* @lock: Lock protecting access to the panthor_fw_csg_input_iface::req
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* field.
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*
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* Needed so we can update the req field concurrently from the interrupt
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* handler and the scheduler logic.
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*
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* TODO: Ideally we'd want to use a cmpxchg() to update the req, but FW
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* interface sections are mapped uncached/write-combined right now, and
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* using cmpxchg() on such mappings leads to SError faults. Revisit when
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* we have 'SHARED' GPU mappings hooked up.
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*/
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spinlock_t lock;
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/**
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* @control: Command stream group slot control interface.
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*
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* Used to expose command stream group slot properties.
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*
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* This interface is read-only.
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*/
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const struct panthor_fw_csg_control_iface *control;
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/**
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* @input: Command stream slot input interface.
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*
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* Used for host updates/events.
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*/
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struct panthor_fw_csg_input_iface *input;
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/**
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* @output: Command stream group slot output interface.
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*
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* Used for FW updates/events.
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*
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* This interface is read-only.
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*/
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const struct panthor_fw_csg_output_iface *output;
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};
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/**
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* struct panthor_fw_global_iface - Firmware global interface
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*/
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struct panthor_fw_global_iface {
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/**
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* @lock: Lock protecting access to the panthor_fw_global_input_iface::req
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* field.
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*
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* Needed so we can update the req field concurrently from the interrupt
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* handler and the scheduler/FW management logic.
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*
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* TODO: Ideally we'd want to use a cmpxchg() to update the req, but FW
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* interface sections are mapped uncached/write-combined right now, and
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* using cmpxchg() on such mappings leads to SError faults. Revisit when
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* we have 'SHARED' GPU mappings hooked up.
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*/
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spinlock_t lock;
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/**
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* @control: Command stream group slot control interface.
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*
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* Used to expose global FW properties.
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*
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* This interface is read-only.
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*/
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const struct panthor_fw_global_control_iface *control;
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/**
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* @input: Global input interface.
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*
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* Used for host updates/events.
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*/
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struct panthor_fw_global_input_iface *input;
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/**
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* @output: Global output interface.
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*
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* Used for FW updates/events.
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*
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* This interface is read-only.
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*/
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const struct panthor_fw_global_output_iface *output;
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};
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/**
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* panthor_fw_toggle_reqs() - Toggle acknowledge bits to send an event to the FW
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* @__iface: The interface to operate on.
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* @__in_reg: Name of the register to update in the input section of the interface.
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* @__out_reg: Name of the register to take as a reference in the output section of the
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* interface.
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* @__mask: Mask to apply to the update.
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*
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* The Host -> FW event/message passing was designed to be lockless, with each side of
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* the channel having its writeable section. Events are signaled as a difference between
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* the host and FW side in the req/ack registers (when a bit differs, there's an event
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* pending, when they are the same, nothing needs attention).
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*
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* This helper allows one to update the req register based on the current value of the
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* ack register managed by the FW. Toggling a specific bit will flag an event. In order
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* for events to be re-evaluated, the interface doorbell needs to be rung.
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*
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* Concurrent accesses to the same req register is covered.
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*
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* Anything requiring atomic updates to multiple registers requires a dedicated lock.
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*/
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#define panthor_fw_toggle_reqs(__iface, __in_reg, __out_reg, __mask) \
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do { \
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u32 __cur_val, __new_val, __out_val; \
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spin_lock(&(__iface)->lock); \
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__cur_val = READ_ONCE((__iface)->input->__in_reg); \
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__out_val = READ_ONCE((__iface)->output->__out_reg); \
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__new_val = ((__out_val ^ (__mask)) & (__mask)) | (__cur_val & ~(__mask)); \
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WRITE_ONCE((__iface)->input->__in_reg, __new_val); \
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spin_unlock(&(__iface)->lock); \
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} while (0)
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/**
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* panthor_fw_update_reqs() - Update bits to reflect a configuration change
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* @__iface: The interface to operate on.
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* @__in_reg: Name of the register to update in the input section of the interface.
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* @__val: Value to set.
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* @__mask: Mask to apply to the update.
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*
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* Some configuration get passed through req registers that are also used to
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* send events to the FW. Those req registers being updated from the interrupt
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* handler, they require special helpers to update the configuration part as well.
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*
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* Concurrent accesses to the same req register is covered.
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*
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* Anything requiring atomic updates to multiple registers requires a dedicated lock.
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*/
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#define panthor_fw_update_reqs(__iface, __in_reg, __val, __mask) \
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do { \
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u32 __cur_val, __new_val; \
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spin_lock(&(__iface)->lock); \
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__cur_val = READ_ONCE((__iface)->input->__in_reg); \
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__new_val = (__cur_val & ~(__mask)) | ((__val) & (__mask)); \
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WRITE_ONCE((__iface)->input->__in_reg, __new_val); \
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spin_unlock(&(__iface)->lock); \
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} while (0)
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struct panthor_fw_global_iface *
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panthor_fw_get_glb_iface(struct panthor_device *ptdev);
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struct panthor_fw_csg_iface *
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panthor_fw_get_csg_iface(struct panthor_device *ptdev, u32 csg_slot);
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struct panthor_fw_cs_iface *
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panthor_fw_get_cs_iface(struct panthor_device *ptdev, u32 csg_slot, u32 cs_slot);
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int panthor_fw_csg_wait_acks(struct panthor_device *ptdev, u32 csg_id, u32 req_mask,
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u32 *acked, u32 timeout_ms);
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int panthor_fw_glb_wait_acks(struct panthor_device *ptdev, u32 req_mask, u32 *acked,
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u32 timeout_ms);
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void panthor_fw_ring_csg_doorbells(struct panthor_device *ptdev, u32 csg_slot);
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struct panthor_kernel_bo *
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panthor_fw_alloc_queue_iface_mem(struct panthor_device *ptdev,
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struct panthor_fw_ringbuf_input_iface **input,
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const struct panthor_fw_ringbuf_output_iface **output,
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u32 *input_fw_va, u32 *output_fw_va);
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struct panthor_kernel_bo *
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panthor_fw_alloc_suspend_buf_mem(struct panthor_device *ptdev, size_t size);
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struct panthor_vm *panthor_fw_vm(struct panthor_device *ptdev);
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void panthor_fw_pre_reset(struct panthor_device *ptdev, bool on_hang);
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int panthor_fw_post_reset(struct panthor_device *ptdev);
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static inline void panthor_fw_suspend(struct panthor_device *ptdev)
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{
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panthor_fw_pre_reset(ptdev, false);
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}
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static inline int panthor_fw_resume(struct panthor_device *ptdev)
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{
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return panthor_fw_post_reset(ptdev);
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}
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int panthor_fw_init(struct panthor_device *ptdev);
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void panthor_fw_unplug(struct panthor_device *ptdev);
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#endif
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