110 lines
3.2 KiB
C
110 lines
3.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
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*/
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#ifndef __DPU_RM_H__
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#define __DPU_RM_H__
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#include <linux/list.h>
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#include "msm_kms.h"
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#include "dpu_hw_top.h"
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struct dpu_global_state;
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/**
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* struct dpu_rm - DPU dynamic hardware resource manager
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* @pingpong_blks: array of pingpong hardware resources
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* @mixer_blks: array of layer mixer hardware resources
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* @ctl_blks: array of ctl hardware resources
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* @hw_intf: array of intf hardware resources
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* @hw_wb: array of wb hardware resources
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* @dspp_blks: array of dspp hardware resources
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* @hw_sspp: array of sspp hardware resources
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* @cdm_blk: cdm hardware resource
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*/
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struct dpu_rm {
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struct dpu_hw_blk *pingpong_blks[PINGPONG_MAX - PINGPONG_0];
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struct dpu_hw_blk *mixer_blks[LM_MAX - LM_0];
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struct dpu_hw_blk *ctl_blks[CTL_MAX - CTL_0];
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struct dpu_hw_intf *hw_intf[INTF_MAX - INTF_0];
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struct dpu_hw_wb *hw_wb[WB_MAX - WB_0];
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struct dpu_hw_blk *dspp_blks[DSPP_MAX - DSPP_0];
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struct dpu_hw_blk *merge_3d_blks[MERGE_3D_MAX - MERGE_3D_0];
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struct dpu_hw_blk *dsc_blks[DSC_MAX - DSC_0];
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struct dpu_hw_sspp *hw_sspp[SSPP_MAX - SSPP_NONE];
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struct dpu_hw_blk *cdm_blk;
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};
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/**
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* struct msm_display_topology - defines a display topology pipeline
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* @num_lm: number of layer mixers used
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* @num_intf: number of interfaces the panel is mounted on
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* @num_dspp: number of dspp blocks used
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* @num_dsc: number of Display Stream Compression (DSC) blocks used
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* @needs_cdm: indicates whether cdm block is needed for this display topology
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*/
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struct msm_display_topology {
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u32 num_lm;
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u32 num_intf;
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u32 num_dspp;
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u32 num_dsc;
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bool needs_cdm;
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};
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int dpu_rm_init(struct drm_device *dev,
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struct dpu_rm *rm,
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const struct dpu_mdss_cfg *cat,
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const struct msm_mdss_data *mdss_data,
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void __iomem *mmio);
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int dpu_rm_reserve(struct dpu_rm *rm,
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struct dpu_global_state *global_state,
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struct drm_encoder *drm_enc,
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struct drm_crtc_state *crtc_state,
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struct msm_display_topology topology);
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void dpu_rm_release(struct dpu_global_state *global_state,
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struct drm_encoder *enc);
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int dpu_rm_get_assigned_resources(struct dpu_rm *rm,
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struct dpu_global_state *global_state, uint32_t enc_id,
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enum dpu_hw_blk_type type, struct dpu_hw_blk **blks, int blks_size);
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void dpu_rm_print_state(struct drm_printer *p,
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const struct dpu_global_state *global_state);
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/**
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* dpu_rm_get_intf - Return a struct dpu_hw_intf instance given it's index.
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* @rm: DPU Resource Manager handle
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* @intf_idx: INTF's index
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*/
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static inline struct dpu_hw_intf *dpu_rm_get_intf(struct dpu_rm *rm, enum dpu_intf intf_idx)
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{
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return rm->hw_intf[intf_idx - INTF_0];
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}
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/**
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* dpu_rm_get_wb - Return a struct dpu_hw_wb instance given it's index.
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* @rm: DPU Resource Manager handle
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* @wb_idx: WB index
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*/
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static inline struct dpu_hw_wb *dpu_rm_get_wb(struct dpu_rm *rm, enum dpu_wb wb_idx)
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{
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return rm->hw_wb[wb_idx - WB_0];
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}
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/**
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* dpu_rm_get_sspp - Return a struct dpu_hw_sspp instance given it's index.
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* @rm: DPU Resource Manager handle
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* @sspp_idx: SSPP index
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*/
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static inline struct dpu_hw_sspp *dpu_rm_get_sspp(struct dpu_rm *rm, enum dpu_sspp sspp_idx)
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{
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return rm->hw_sspp[sspp_idx - SSPP_NONE];
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}
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#endif /* __DPU_RM_H__ */
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