217 lines
7.1 KiB
C
217 lines
7.1 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2019 Intel Corporation
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*/
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#ifndef __INTEL_GT__
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#define __INTEL_GT__
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#include "intel_engine_types.h"
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#include "intel_gt_types.h"
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#include "intel_reset.h"
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struct drm_i915_private;
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struct drm_printer;
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/*
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* Check that the GT is a graphics GT and has an IP version within the
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* specified range (inclusive).
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*/
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#define IS_GFX_GT_IP_RANGE(gt, from, until) ( \
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BUILD_BUG_ON_ZERO((from) < IP_VER(2, 0)) + \
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BUILD_BUG_ON_ZERO((until) < (from)) + \
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((gt)->type != GT_MEDIA && \
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GRAPHICS_VER_FULL((gt)->i915) >= (from) && \
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GRAPHICS_VER_FULL((gt)->i915) <= (until)))
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/*
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* Check that the GT is a media GT and has an IP version within the
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* specified range (inclusive).
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*
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* Only usable on platforms with a standalone media design (i.e., IP version 13
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* and higher).
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*/
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#define IS_MEDIA_GT_IP_RANGE(gt, from, until) ( \
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BUILD_BUG_ON_ZERO((from) < IP_VER(13, 0)) + \
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BUILD_BUG_ON_ZERO((until) < (from)) + \
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((gt) && (gt)->type == GT_MEDIA && \
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MEDIA_VER_FULL((gt)->i915) >= (from) && \
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MEDIA_VER_FULL((gt)->i915) <= (until)))
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/*
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* Check that the GT is a graphics GT with a specific IP version and has
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* a stepping in the range [from, until). The lower stepping bound is
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* inclusive, the upper bound is exclusive. The most common use-case of this
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* macro is for checking bounds for workarounds, which usually have a stepping
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* ("from") at which the hardware issue is first present and another stepping
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* ("until") at which a hardware fix is present and the software workaround is
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* no longer necessary. E.g.,
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*
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* IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0)
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* IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_B1, STEP_FOREVER)
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*
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* "STEP_FOREVER" can be passed as "until" for workarounds that have no upper
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* stepping bound for the specified IP version.
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*/
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#define IS_GFX_GT_IP_STEP(gt, ipver, from, until) ( \
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BUILD_BUG_ON_ZERO((until) <= (from)) + \
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(IS_GFX_GT_IP_RANGE((gt), (ipver), (ipver)) && \
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IS_GRAPHICS_STEP((gt)->i915, (from), (until))))
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/*
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* Check that the GT is a media GT with a specific IP version and has
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* a stepping in the range [from, until). The lower stepping bound is
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* inclusive, the upper bound is exclusive. The most common use-case of this
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* macro is for checking bounds for workarounds, which usually have a stepping
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* ("from") at which the hardware issue is first present and another stepping
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* ("until") at which a hardware fix is present and the software workaround is
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* no longer necessary. "STEP_FOREVER" can be passed as "until" for
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* workarounds that have no upper stepping bound for the specified IP version.
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*
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* This macro may only be used to match on platforms that have a standalone
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* media design (i.e., media version 13 or higher).
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*/
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#define IS_MEDIA_GT_IP_STEP(gt, ipver, from, until) ( \
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BUILD_BUG_ON_ZERO((until) <= (from)) + \
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(IS_MEDIA_GT_IP_RANGE((gt), (ipver), (ipver)) && \
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IS_MEDIA_STEP((gt)->i915, (from), (until))))
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#define GT_TRACE(gt, fmt, ...) do { \
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const struct intel_gt *gt__ __maybe_unused = (gt); \
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GEM_TRACE("%s " fmt, dev_name(gt__->i915->drm.dev), \
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##__VA_ARGS__); \
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} while (0)
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static inline bool gt_is_root(struct intel_gt *gt)
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{
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return !gt->info.id;
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}
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bool intel_gt_needs_wa_16018031267(struct intel_gt *gt);
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bool intel_gt_needs_wa_22016122933(struct intel_gt *gt);
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#define NEEDS_FASTCOLOR_BLT_WABB(engine) ( \
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intel_gt_needs_wa_16018031267(engine->gt) && \
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engine->class == COPY_ENGINE_CLASS && engine->instance == 0)
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static inline struct intel_gt *uc_to_gt(struct intel_uc *uc)
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{
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return container_of(uc, struct intel_gt, uc);
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}
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static inline struct intel_gt *guc_to_gt(struct intel_guc *guc)
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{
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return container_of(guc, struct intel_gt, uc.guc);
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}
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static inline struct intel_gt *huc_to_gt(struct intel_huc *huc)
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{
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return container_of(huc, struct intel_gt, uc.huc);
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}
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static inline struct intel_gt *gsc_uc_to_gt(struct intel_gsc_uc *gsc_uc)
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{
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return container_of(gsc_uc, struct intel_gt, uc.gsc);
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}
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static inline struct intel_gt *gsc_to_gt(struct intel_gsc *gsc)
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{
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return container_of(gsc, struct intel_gt, gsc);
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}
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static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
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{
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return guc_to_gt(guc)->i915;
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}
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static inline struct intel_guc *gt_to_guc(struct intel_gt *gt)
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{
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return >->uc.guc;
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}
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void intel_gt_common_init_early(struct intel_gt *gt);
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int intel_root_gt_init_early(struct drm_i915_private *i915);
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int intel_gt_assign_ggtt(struct intel_gt *gt);
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int intel_gt_init_mmio(struct intel_gt *gt);
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int __must_check intel_gt_init_hw(struct intel_gt *gt);
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int intel_gt_init(struct intel_gt *gt);
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void intel_gt_driver_register(struct intel_gt *gt);
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void intel_gt_driver_unregister(struct intel_gt *gt);
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void intel_gt_driver_remove(struct intel_gt *gt);
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void intel_gt_driver_release(struct intel_gt *gt);
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void intel_gt_driver_late_release_all(struct drm_i915_private *i915);
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int intel_gt_wait_for_idle(struct intel_gt *gt, long timeout);
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void intel_gt_check_and_clear_faults(struct intel_gt *gt);
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i915_reg_t intel_gt_perf_limit_reasons_reg(struct intel_gt *gt);
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void intel_gt_clear_error_registers(struct intel_gt *gt,
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intel_engine_mask_t engine_mask);
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void intel_gt_flush_ggtt_writes(struct intel_gt *gt);
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void intel_gt_chipset_flush(struct intel_gt *gt);
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static inline u32 intel_gt_scratch_offset(const struct intel_gt *gt,
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enum intel_gt_scratch_field field)
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{
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return i915_ggtt_offset(gt->scratch) + field;
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}
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static inline bool intel_gt_has_unrecoverable_error(const struct intel_gt *gt)
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{
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return test_bit(I915_WEDGED_ON_INIT, >->reset.flags) ||
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test_bit(I915_WEDGED_ON_FINI, >->reset.flags);
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}
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static inline bool intel_gt_is_wedged(const struct intel_gt *gt)
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{
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GEM_BUG_ON(intel_gt_has_unrecoverable_error(gt) &&
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!test_bit(I915_WEDGED, >->reset.flags));
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return unlikely(test_bit(I915_WEDGED, >->reset.flags));
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}
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int intel_gt_probe_all(struct drm_i915_private *i915);
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int intel_gt_tiles_init(struct drm_i915_private *i915);
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#define for_each_gt(gt__, i915__, id__) \
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for ((id__) = 0; \
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(id__) < I915_MAX_GT; \
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(id__)++) \
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for_each_if(((gt__) = (i915__)->gt[(id__)]))
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/* Simple iterator over all initialised engines */
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#define for_each_engine(engine__, gt__, id__) \
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for ((id__) = 0; \
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(id__) < I915_NUM_ENGINES; \
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(id__)++) \
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for_each_if ((engine__) = (gt__)->engine[(id__)])
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/* Iterator over subset of engines selected by mask */
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#define for_each_engine_masked(engine__, gt__, mask__, tmp__) \
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for ((tmp__) = (mask__) & (gt__)->info.engine_mask; \
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(tmp__) ? \
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((engine__) = (gt__)->engine[__mask_next_bit(tmp__)]), 1 : \
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0;)
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void intel_gt_info_print(const struct intel_gt_info *info,
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struct drm_printer *p);
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void intel_gt_watchdog_work(struct work_struct *work);
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enum i915_map_type intel_gt_coherent_map_type(struct intel_gt *gt,
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struct drm_i915_gem_object *obj,
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bool always_coherent);
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void intel_gt_bind_context_set_ready(struct intel_gt *gt);
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void intel_gt_bind_context_set_unready(struct intel_gt *gt);
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bool intel_gt_is_bind_context_ready(struct intel_gt *gt);
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static inline void intel_gt_set_wedged_async(struct intel_gt *gt)
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{
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queue_work(system_highpri_wq, >->wedge);
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}
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#endif /* __INTEL_GT_H__ */
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