159 lines
4.0 KiB
C
159 lines
4.0 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2022 Pengutronix, Lucas Stach <kernel@pengutronix.de>
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*/
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#include <linux/clk.h>
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <drm/bridge/dw_hdmi.h>
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#include <drm/drm_modes.h>
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struct imx8mp_hdmi {
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struct dw_hdmi_plat_data plat_data;
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struct dw_hdmi *dw_hdmi;
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struct clk *pixclk;
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};
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static enum drm_mode_status
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imx8mp_hdmi_mode_valid(struct dw_hdmi *dw_hdmi, void *data,
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const struct drm_display_info *info,
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const struct drm_display_mode *mode)
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{
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struct imx8mp_hdmi *hdmi = (struct imx8mp_hdmi *)data;
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long round_rate;
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if (mode->clock < 13500)
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return MODE_CLOCK_LOW;
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if (mode->clock > 297000)
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return MODE_CLOCK_HIGH;
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round_rate = clk_round_rate(hdmi->pixclk, mode->clock * 1000);
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/* imx8mp's pixel clock generator (fsl-samsung-hdmi) cannot generate
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* all possible frequencies, so allow some tolerance to support more
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* modes.
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* Allow 0.5% difference allowed in various standards (VESA, CEA861)
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* 0.5% = 5/1000 tolerance (mode->clock is 1/1000)
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*/
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if (abs(round_rate - mode->clock * 1000) > mode->clock * 5)
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return MODE_CLOCK_RANGE;
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/* We don't support double-clocked and Interlaced modes */
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if ((mode->flags & DRM_MODE_FLAG_DBLCLK) ||
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(mode->flags & DRM_MODE_FLAG_INTERLACE))
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return MODE_BAD;
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return MODE_OK;
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}
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static int imx8mp_hdmi_phy_init(struct dw_hdmi *dw_hdmi, void *data,
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const struct drm_display_info *display,
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const struct drm_display_mode *mode)
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{
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return 0;
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}
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static void imx8mp_hdmi_phy_disable(struct dw_hdmi *dw_hdmi, void *data)
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{
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}
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static void im8mp_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data)
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{
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/*
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* Just release PHY core from reset, all other power management is done
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* by the PHY driver.
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*/
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dw_hdmi_phy_gen1_reset(hdmi);
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dw_hdmi_phy_setup_hpd(hdmi, data);
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}
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static const struct dw_hdmi_phy_ops imx8mp_hdmi_phy_ops = {
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.init = imx8mp_hdmi_phy_init,
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.disable = imx8mp_hdmi_phy_disable,
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.setup_hpd = im8mp_hdmi_phy_setup_hpd,
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.read_hpd = dw_hdmi_phy_read_hpd,
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.update_hpd = dw_hdmi_phy_update_hpd,
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};
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static int imx8mp_dw_hdmi_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct dw_hdmi_plat_data *plat_data;
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struct imx8mp_hdmi *hdmi;
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hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
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if (!hdmi)
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return -ENOMEM;
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plat_data = &hdmi->plat_data;
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hdmi->pixclk = devm_clk_get(dev, "pix");
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if (IS_ERR(hdmi->pixclk))
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return dev_err_probe(dev, PTR_ERR(hdmi->pixclk),
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"Unable to get pixel clock\n");
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plat_data->mode_valid = imx8mp_hdmi_mode_valid;
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plat_data->phy_ops = &imx8mp_hdmi_phy_ops;
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plat_data->phy_name = "SAMSUNG HDMI TX PHY";
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plat_data->priv_data = hdmi;
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plat_data->phy_force_vendor = true;
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hdmi->dw_hdmi = dw_hdmi_probe(pdev, plat_data);
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if (IS_ERR(hdmi->dw_hdmi))
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return PTR_ERR(hdmi->dw_hdmi);
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platform_set_drvdata(pdev, hdmi);
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return 0;
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}
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static void imx8mp_dw_hdmi_remove(struct platform_device *pdev)
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{
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struct imx8mp_hdmi *hdmi = platform_get_drvdata(pdev);
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dw_hdmi_remove(hdmi->dw_hdmi);
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}
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static int imx8mp_dw_hdmi_pm_suspend(struct device *dev)
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{
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return 0;
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}
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static int imx8mp_dw_hdmi_pm_resume(struct device *dev)
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{
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struct imx8mp_hdmi *hdmi = dev_get_drvdata(dev);
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dw_hdmi_resume(hdmi->dw_hdmi);
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return 0;
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}
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static const struct dev_pm_ops imx8mp_dw_hdmi_pm_ops = {
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SYSTEM_SLEEP_PM_OPS(imx8mp_dw_hdmi_pm_suspend, imx8mp_dw_hdmi_pm_resume)
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};
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static const struct of_device_id imx8mp_dw_hdmi_of_table[] = {
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{ .compatible = "fsl,imx8mp-hdmi-tx" },
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{ /* Sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, imx8mp_dw_hdmi_of_table);
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static struct platform_driver imx8mp_dw_hdmi_platform_driver = {
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.probe = imx8mp_dw_hdmi_probe,
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.remove = imx8mp_dw_hdmi_remove,
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.driver = {
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.name = "imx8mp-dw-hdmi-tx",
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.of_match_table = imx8mp_dw_hdmi_of_table,
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.pm = pm_ptr(&imx8mp_dw_hdmi_pm_ops),
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},
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};
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module_platform_driver(imx8mp_dw_hdmi_platform_driver);
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MODULE_DESCRIPTION("i.MX8MP HDMI encoder driver");
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MODULE_LICENSE("GPL");
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