98 lines
3.8 KiB
C
98 lines
3.8 KiB
C
/*
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* Copyright 2023 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __UMC_V12_0_H__
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#define __UMC_V12_0_H__
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#include "soc15_common.h"
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#include "amdgpu.h"
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#define UMC_V12_0_NODE_DIST 0x40000000
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#define UMC_V12_0_INST_DIST 0x40000
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/* UMC register per channel offset */
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#define UMC_V12_0_PER_CHANNEL_OFFSET 0x400
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/* UMC cross node offset */
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#define UMC_V12_0_CROSS_NODE_OFFSET 0x100000000
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/* OdEccErrCnt max value */
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#define UMC_V12_0_CE_CNT_MAX 0xffff
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/* umc ce interrupt threshold */
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#define UMC_V12_0_CE_INT_THRESHOLD 0xffff
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/* umc ce count initial value */
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#define UMC_V12_0_CE_CNT_INIT (UMC_V12_0_CE_CNT_MAX - UMC_V12_0_CE_INT_THRESHOLD)
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/* number of umc channel instance with memory map register access */
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#define UMC_V12_0_CHANNEL_INSTANCE_NUM 8
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/* number of umc instance with memory map register access */
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#define UMC_V12_0_UMC_INSTANCE_NUM 4
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/* Total channel instances for all available umc nodes */
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#define UMC_V12_0_TOTAL_CHANNEL_NUM(adev) \
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(UMC_V12_0_CHANNEL_INSTANCE_NUM * (adev)->gmc.num_umc)
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/* one piece of normalized address is mapped to 8 pieces of physical address */
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#define UMC_V12_0_NA_MAP_PA_NUM 8
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/* R13 bit shift should be considered, double the number */
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#define UMC_V12_0_BAD_PAGE_NUM_PER_CHANNEL (UMC_V12_0_NA_MAP_PA_NUM * 2)
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/* column bits in SOC physical address */
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#define UMC_V12_0_PA_C2_BIT 15
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#define UMC_V12_0_PA_C4_BIT 21
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/* row bits in SOC physical address */
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#define UMC_V12_0_PA_R13_BIT 35
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#define MCA_UMC_HWID_V12_0 0x96
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#define MCA_UMC_MCATYPE_V12_0 0x0
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#define MCA_IPID_LO_2_UMC_CH(_ipid_lo) (((((_ipid_lo) >> 20) & 0x1) * 4) + \
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(((_ipid_lo) >> 12) & 0xF))
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#define MCA_IPID_LO_2_UMC_INST(_ipid_lo) (((_ipid_lo) >> 21) & 0x7)
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#define MCA_IPID_2_DIE_ID(ipid) ((REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdHi) >> 2) & 0x03)
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#define MCA_IPID_2_UMC_CH(ipid) \
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(MCA_IPID_LO_2_UMC_CH(REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdLo)))
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#define MCA_IPID_2_UMC_INST(ipid) \
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(MCA_IPID_LO_2_UMC_INST(REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdLo)))
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#define MCA_IPID_2_SOCKET_ID(ipid) \
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(((REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdLo) & 0x1) << 2) | \
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(REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdHi) & 0x03))
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#define UMC_V12_ADDR_MASK_BAD_COLS(addr) \
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((addr) & ~((0x3ULL << UMC_V12_0_PA_C2_BIT) | \
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(0x1ULL << UMC_V12_0_PA_C4_BIT) | \
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(0x1ULL << UMC_V12_0_PA_R13_BIT)))
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bool umc_v12_0_is_deferred_error(struct amdgpu_device *adev, uint64_t mc_umc_status);
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bool umc_v12_0_is_uncorrectable_error(struct amdgpu_device *adev, uint64_t mc_umc_status);
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bool umc_v12_0_is_correctable_error(struct amdgpu_device *adev, uint64_t mc_umc_status);
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typedef bool (*check_error_type_func)(struct amdgpu_device *adev, uint64_t mc_umc_status);
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extern struct amdgpu_umc_ras umc_v12_0_ras;
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#endif
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