170 lines
5.9 KiB
C
170 lines
5.9 KiB
C
/*
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* Copyright (C) 2021 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
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* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef __AMDGPU_MCA_H__
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#define __AMDGPU_MCA_H__
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#include "amdgpu_ras.h"
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#define MCA_MAX_REGS_COUNT (16)
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#define MCA_REG_FIELD(x, h, l) (((x) & GENMASK_ULL(h, l)) >> l)
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#define MCA_REG__STATUS__VAL(x) MCA_REG_FIELD(x, 63, 63)
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#define MCA_REG__STATUS__OVERFLOW(x) MCA_REG_FIELD(x, 62, 62)
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#define MCA_REG__STATUS__UC(x) MCA_REG_FIELD(x, 61, 61)
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#define MCA_REG__STATUS__EN(x) MCA_REG_FIELD(x, 60, 60)
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#define MCA_REG__STATUS__MISCV(x) MCA_REG_FIELD(x, 59, 59)
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#define MCA_REG__STATUS__ADDRV(x) MCA_REG_FIELD(x, 58, 58)
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#define MCA_REG__STATUS__PCC(x) MCA_REG_FIELD(x, 57, 57)
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#define MCA_REG__STATUS__ERRCOREIDVAL(x) MCA_REG_FIELD(x, 56, 56)
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#define MCA_REG__STATUS__TCC(x) MCA_REG_FIELD(x, 55, 55)
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#define MCA_REG__STATUS__SYNDV(x) MCA_REG_FIELD(x, 53, 53)
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#define MCA_REG__STATUS__CECC(x) MCA_REG_FIELD(x, 46, 46)
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#define MCA_REG__STATUS__UECC(x) MCA_REG_FIELD(x, 45, 45)
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#define MCA_REG__STATUS__DEFERRED(x) MCA_REG_FIELD(x, 44, 44)
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#define MCA_REG__STATUS__POISON(x) MCA_REG_FIELD(x, 43, 43)
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#define MCA_REG__STATUS__SCRUB(x) MCA_REG_FIELD(x, 40, 40)
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#define MCA_REG__STATUS__ERRCOREID(x) MCA_REG_FIELD(x, 37, 32)
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#define MCA_REG__STATUS__ADDRLSB(x) MCA_REG_FIELD(x, 29, 24)
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#define MCA_REG__STATUS__ERRORCODEEXT(x) MCA_REG_FIELD(x, 21, 16)
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#define MCA_REG__STATUS__ERRORCODE(x) MCA_REG_FIELD(x, 15, 0)
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#define MCA_REG__MISC0__ERRCNT(x) MCA_REG_FIELD(x, 43, 32)
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#define MCA_REG__SYND__ERRORINFORMATION(x) MCA_REG_FIELD(x, 17, 0)
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enum amdgpu_mca_ip {
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AMDGPU_MCA_IP_UNKNOW = -1,
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AMDGPU_MCA_IP_PSP = 0,
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AMDGPU_MCA_IP_SDMA,
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AMDGPU_MCA_IP_GC,
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AMDGPU_MCA_IP_SMU,
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AMDGPU_MCA_IP_MP5,
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AMDGPU_MCA_IP_UMC,
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AMDGPU_MCA_IP_PCS_XGMI,
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AMDGPU_MCA_IP_COUNT,
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};
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enum amdgpu_mca_error_type {
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AMDGPU_MCA_ERROR_TYPE_UE = 0,
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AMDGPU_MCA_ERROR_TYPE_CE,
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AMDGPU_MCA_ERROR_TYPE_DE,
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};
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struct amdgpu_mca_ras_block {
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struct amdgpu_ras_block_object ras_block;
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};
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struct amdgpu_mca_ras {
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struct ras_common_if *ras_if;
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struct amdgpu_mca_ras_block *ras;
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};
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struct mca_bank_set {
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int nr_entries;
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struct list_head list;
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};
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struct mca_bank_cache {
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struct mca_bank_set mca_set;
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struct mutex lock;
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};
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struct amdgpu_mca {
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struct amdgpu_mca_ras mp0;
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struct amdgpu_mca_ras mp1;
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struct amdgpu_mca_ras mpio;
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const struct amdgpu_mca_smu_funcs *mca_funcs;
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struct mca_bank_cache mca_caches[AMDGPU_MCA_ERROR_TYPE_DE];
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atomic_t ue_update_flag;
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};
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enum mca_reg_idx {
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MCA_REG_IDX_STATUS = 1,
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MCA_REG_IDX_ADDR = 2,
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MCA_REG_IDX_MISC0 = 3,
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MCA_REG_IDX_IPID = 5,
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MCA_REG_IDX_SYND = 6,
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MCA_REG_IDX_COUNT = 16,
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};
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struct mca_bank_info {
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int socket_id;
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int aid;
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int hwid;
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int mcatype;
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};
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struct mca_bank_entry {
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int idx;
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enum amdgpu_mca_error_type type;
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enum amdgpu_mca_ip ip;
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struct mca_bank_info info;
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uint64_t regs[MCA_MAX_REGS_COUNT];
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};
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struct mca_bank_node {
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struct mca_bank_entry entry;
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struct list_head node;
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};
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struct amdgpu_mca_smu_funcs {
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int max_ue_count;
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int max_ce_count;
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int (*mca_set_debug_mode)(struct amdgpu_device *adev, bool enable);
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int (*mca_parse_mca_error_count)(struct amdgpu_device *adev, enum amdgpu_ras_block blk, enum amdgpu_mca_error_type type,
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struct mca_bank_entry *entry, uint32_t *count);
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int (*mca_get_valid_mca_count)(struct amdgpu_device *adev, enum amdgpu_mca_error_type type,
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uint32_t *count);
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int (*mca_get_mca_entry)(struct amdgpu_device *adev, enum amdgpu_mca_error_type type,
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int idx, struct mca_bank_entry *entry);
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};
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void amdgpu_mca_query_correctable_error_count(struct amdgpu_device *adev,
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uint64_t mc_status_addr,
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unsigned long *error_count);
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void amdgpu_mca_query_uncorrectable_error_count(struct amdgpu_device *adev,
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uint64_t mc_status_addr,
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unsigned long *error_count);
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void amdgpu_mca_reset_error_count(struct amdgpu_device *adev,
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uint64_t mc_status_addr);
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void amdgpu_mca_query_ras_error_count(struct amdgpu_device *adev,
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uint64_t mc_status_addr,
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void *ras_error_status);
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int amdgpu_mca_mp0_ras_sw_init(struct amdgpu_device *adev);
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int amdgpu_mca_mp1_ras_sw_init(struct amdgpu_device *adev);
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int amdgpu_mca_mpio_ras_sw_init(struct amdgpu_device *adev);
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void amdgpu_mca_smu_init_funcs(struct amdgpu_device *adev, const struct amdgpu_mca_smu_funcs *mca_funcs);
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int amdgpu_mca_init(struct amdgpu_device *adev);
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void amdgpu_mca_fini(struct amdgpu_device *adev);
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int amdgpu_mca_reset(struct amdgpu_device *adev);
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int amdgpu_mca_smu_set_debug_mode(struct amdgpu_device *adev, bool enable);
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int amdgpu_mca_smu_get_mca_set_error_count(struct amdgpu_device *adev, enum amdgpu_ras_block blk,
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enum amdgpu_mca_error_type type, uint32_t *total);
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void amdgpu_mca_smu_debugfs_init(struct amdgpu_device *adev, struct dentry *root);
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int amdgpu_mca_smu_log_ras_error(struct amdgpu_device *adev, enum amdgpu_ras_block blk, enum amdgpu_mca_error_type type,
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struct ras_err_data *err_data, struct ras_query_context *qctx);
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#endif
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