88 lines
1.9 KiB
Plaintext
88 lines
1.9 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-only OR MIT
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/*
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* DT overlay for PCIe support (limits USB to 2.0/high-speed)
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*
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* Copyright (C) 2021 PHYTEC America, LLC - https://www.phytec.com
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* Author: Matt McKee <mmckee@phytec.com>
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*
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* Copyright (C) 2024 PHYTEC America, LLC - https://www.phytec.com
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* Author: Nathan Morrisson <nmorrisson@phytec.com>
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*/
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/dts-v1/;
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/plugin/;
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/phy/phy-cadence.h>
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#include "k3-pinctrl.h"
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#include "k3-serdes.h"
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&{/} {
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pcie_refclk0: pcie-refclk0 {
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compatible = "gpio-gate-clock";
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pinctrl-names = "default";
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pinctrl-0 = <&pcie_usb_sel_pins_default>;
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clocks = <&serdes_refclk>;
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#clock-cells = <0>;
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enable-gpios = <&main_gpio1 7 GPIO_ACTIVE_HIGH>;
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};
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};
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&main_pmx0 {
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pcie_usb_sel_pins_default: pcie-usb-sel-default-pins {
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pinctrl-single,pins = <
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AM64X_IOPAD(0x017c, PIN_OUTPUT, 7) /* (T1) PRG0_PRU0_GPO7.GPIO1_7 */
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>;
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};
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pcie_pins_default: pcie-default-pins {
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pinctrl-single,pins = <
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AM64X_IOPAD(0x0098, PIN_OUTPUT, 7) /* (W19) GPMC0_WAIT0.GPIO0_37 */
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>;
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};
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};
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&pcie0_rc {
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pinctrl-names = "default";
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pinctrl-0 = <&pcie_pins_default>;
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reset-gpios = <&main_gpio0 37 GPIO_ACTIVE_HIGH>;
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phys = <&serdes0_pcie_usb_link>;
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phy-names = "pcie-phy";
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num-lanes = <1>;
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status = "okay";
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};
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&serdes0_pcie_usb_link {
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cdns,phy-type = <PHY_TYPE_PCIE>;
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};
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&serdes_ln_ctrl {
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idle-states = <AM64_SERDES0_LANE0_PCIE0>;
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};
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&serdes0 {
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assigned-clock-parents = <&pcie_refclk0>, <&pcie_refclk0>, <&pcie_refclk0>;
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};
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&serdes_refclk {
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clock-frequency = <100000000>;
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};
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/*
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* Assign pcie_refclk0 to serdes_wiz0 as ext_ref_clk.
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* This makes sure that the clock generator gets enabled at the right time.
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*/
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&serdes_wiz0 {
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clocks = <&k3_clks 162 0>, <&k3_clks 162 1>, <&pcie_refclk0>;
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};
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&usbss0 {
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ti,usb2-only;
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};
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&usb0 {
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maximum-speed = "high-speed";
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};
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