555 lines
15 KiB
Plaintext
555 lines
15 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0-or-later OR X11)
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/*
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* Copyright 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
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* D-82229 Seefeld, Germany.
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* Author: Alexander Stein
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*/
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/leds/common.h>
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#include <dt-bindings/net/ti-dp83867.h>
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/ {
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adc {
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compatible = "iio-hwmon";
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io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>;
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};
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aliases {
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rtc0 = &pcf85063;
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rtc1 = &rtc;
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};
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backlight_lvds: backlight-lvds {
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compatible = "pwm-backlight";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_bl_lvds>;
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pwms = <&adma_pwm 0 5000000 0>;
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brightness-levels = <0 4 8 16 32 64 128 255>;
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default-brightness-level = <7>;
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power-supply = <®_12v0>;
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enable-gpios = <&lsio_gpio1 30 GPIO_ACTIVE_HIGH>;
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status = "disabled";
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};
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chosen {
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stdout-path = &lpuart1;
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};
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gpio-keys {
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compatible = "gpio-keys";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpiobuttons>;
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autorepeat;
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switch-a {
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label = "switcha";
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linux,code = <BTN_0>;
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gpios = <&lsio_gpio1 13 GPIO_ACTIVE_LOW>;
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};
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switch-b {
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label = "switchb";
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linux,code = <BTN_1>;
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gpios = <&lsio_gpio1 14 GPIO_ACTIVE_LOW>;
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};
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};
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gpio-leds {
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compatible = "gpio-leds";
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led1 {
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_STATUS;
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gpios = <&expander 1 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "default-on";
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};
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led2 {
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_HEARTBEAT;
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gpios = <&expander 2 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "heartbeat";
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};
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};
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/* TODO LVDS panels */
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reg_12v0: regulator-12v0 {
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compatible = "regulator-fixed";
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regulator-name = "V_12V";
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regulator-min-microvolt = <12000000>;
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regulator-max-microvolt = <12000000>;
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gpio = <&expander 6 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_pcie_1v5: regulator-pcie-1v5 {
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compatible = "regulator-fixed";
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regulator-name = "MBA8XX_PCIE_1V5";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_reg_pcie_1v5>;
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regulator-min-microvolt = <1500000>;
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regulator-max-microvolt = <1500000>;
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gpio = <&lsio_gpio0 30 GPIO_ACTIVE_HIGH>;
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startup-delay-us = <1000>;
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enable-active-high;
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};
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reg_pcie_3v3: regulator-pcie-3v3 {
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compatible = "regulator-fixed";
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regulator-name = "MBA8XX_PCIE_3V3";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_reg_pcie_3v3>;
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&lsio_gpio0 31 GPIO_ACTIVE_HIGH>;
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startup-delay-us = <1000>;
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enable-active-high;
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regulator-always-on;
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};
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reg_3v3_mb: regulator-usdhc2-vmmc {
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compatible = "regulator-fixed";
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regulator-name = "V_3V3_MB";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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sound {
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compatible = "fsl,imx-audio-tlv320aic32x4";
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model = "tqm-tlv320aic32";
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audio-codec = <&tlv320aic3x04>;
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ssi-controller = <&sai1>;
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};
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};
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&adc0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_adc0>;
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vref-supply = <®_1v8>;
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#io-channel-cells = <1>;
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status = "okay";
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};
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&adma_pwm {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_admapwm>;
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec1>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy0>;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ethphy0>;
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ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
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ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
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ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
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ti,dp83867-rxctrl-strap-quirk;
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ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
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reset-gpios = <&lsio_gpio3 2 GPIO_ACTIVE_LOW>;
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reset-assert-us = <500000>;
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reset-deassert-us = <50000>;
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enet-phy-lane-no-swap;
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interrupt-parent = <&lsio_gpio3>;
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interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
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};
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ethphy3: ethernet-phy@3 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <3>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ethphy3>;
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ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
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ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
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ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
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ti,dp83867-rxctrl-strap-quirk;
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ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
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reset-gpios = <&lsio_gpio3 3 GPIO_ACTIVE_LOW>;
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reset-assert-us = <500000>;
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reset-deassert-us = <50000>;
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enet-phy-lane-no-swap;
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interrupt-parent = <&lsio_gpio3>;
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interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
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};
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};
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};
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&fec2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec2>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy3>;
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status = "okay";
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};
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&flexcan1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_can0>;
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xceiver-supply = <®_3v3>;
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status = "okay";
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};
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&flexcan2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_can1>;
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xceiver-supply = <®_3v3>;
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status = "okay";
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};
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&i2c1 {
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tlv320aic3x04: audio-codec@18 {
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compatible = "ti,tlv320aic32x4";
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reg = <0x18>;
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clocks = <&mclkout0_lpcg 0>;
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clock-names = "mclk";
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iov-supply = <®_1v8>;
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ldoin-supply = <®_3v3>;
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};
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se97b_1c: temperature-sensor@1c {
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compatible = "nxp,se97b", "jedec,jc-42.4-temp";
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reg = <0x1c>;
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};
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at24c02_54: eeprom@54 {
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compatible = "nxp,se97b", "atmel,24c02";
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reg = <0x54>;
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pagesize = <16>;
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vcc-supply = <®_3v3>;
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};
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expander: gpio@70 {
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compatible = "nxp,pca9538";
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reg = <0x70>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pca9538>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-parent = <&lsio_gpio4>;
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interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
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interrupt-controller;
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#interrupt-cells = <2>;
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vcc-supply = <®_1v8>;
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gpio-line-names = "", "LED_A",
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"LED_B", "",
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"DSI_EN", "USB_RESET#",
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"V_12V_EN", "PCIE_DIS#";
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};
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};
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&i2c2 {
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clock-frequency = <100000>;
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_lpi2c2>;
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pinctrl-1 = <&pinctrl_lpi2c2gpio>;
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scl-gpios = <&lsio_gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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sda-gpios = <&lsio_gpio2 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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status = "okay";
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};
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/* TODO LDB */
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&lpspi1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_spi1>;
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cs-gpios = <&lsio_gpio0 27 GPIO_ACTIVE_LOW>, <&lsio_gpio0 29 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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&lpspi2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_spi2>;
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cs-gpios = <&lsio_gpio1 0 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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&lpspi3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_spi3>;
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num-cs = <2>;
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cs-gpios = <&lsio_gpio0 16 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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&lpuart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lpuart1>;
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status = "okay";
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};
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&lpuart3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lpuart3>;
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status = "okay";
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};
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&lsio_gpio3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lsgpio3>;
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gpio-line-names = "", "", "", "",
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"", "", "", "",
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"", "", "", "",
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"", "", "", "X4_15",
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"", "", "", "",
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"", "", "", "",
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"", "", "", "",
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"", "", "", "";
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};
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/* TODO: Mini-PCIe */
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&sai1 {
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assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
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<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
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<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
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<&sai1_lpcg 0>;
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assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sai1>;
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status = "okay";
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};
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&usbotg1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usbotg1>;
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srp-disable;
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hnp-disable;
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adp-disable;
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power-active-high;
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over-current-active-low;
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dr_mode = "otg";
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status = "okay";
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};
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&usbotg3 {
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status = "okay";
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};
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&usbotg3_cdns3 {
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dr_mode = "host";
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status = "okay";
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};
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&usbphy1 {
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status = "okay";
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};
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&usb3_phy {
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status = "okay";
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};
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&usdhc2 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
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pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
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pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
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bus-width = <4>;
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cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>;
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wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>;
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vmmc-supply = <®_3v3_mb>;
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no-1-8-v;
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no-sdio;
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no-mmc;
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status = "okay";
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};
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&iomuxc {
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pinctrl_adc0: adc0grp {
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fsl,pins = <IMX8QXP_ADC_IN0_ADMA_ADC_IN0 0x02000060>,
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<IMX8QXP_ADC_IN1_ADMA_ADC_IN1 0x02000060>,
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<IMX8QXP_ADC_IN2_ADMA_ADC_IN2 0x02000060>,
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<IMX8QXP_ADC_IN3_ADMA_ADC_IN3 0x02000060>;
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};
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pinctrl_admapwm: admapwmgrp {
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fsl,pins = <IMX8QXP_SPI0_CS1_ADMA_LCD_PWM0_OUT 0x00000021>;
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};
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pinctrl_bl_lvds: bllvdsgrp {
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fsl,pins = <IMX8QXP_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO30 0x00000021>;
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};
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pinctrl_can0: can0grp {
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fsl,pins = <IMX8QXP_UART0_RX_ADMA_FLEXCAN0_RX 0x00000021>,
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<IMX8QXP_UART0_TX_ADMA_FLEXCAN0_TX 0x00000021>;
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};
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pinctrl_can1: can1grp {
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fsl,pins = <IMX8QXP_UART2_RX_ADMA_FLEXCAN1_RX 0x00000021>,
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<IMX8QXP_UART2_TX_ADMA_FLEXCAN1_TX 0x00000021>;
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};
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pinctrl_ethphy0: ethphy0grp {
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fsl,pins = <IMX8QXP_CSI_EN_LSIO_GPIO3_IO02 0x00000040>,
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<IMX8QXP_CSI_PCLK_LSIO_GPIO3_IO00 0x00000040>;
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};
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pinctrl_ethphy3: ethphy3grp {
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fsl,pins = <IMX8QXP_CSI_RESET_LSIO_GPIO3_IO03 0x00000040>,
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<IMX8QXP_CSI_MCLK_LSIO_GPIO3_IO01 0x00000040>;
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};
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pinctrl_fec1: fec1grp {
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fsl,pins = <IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000041>,
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<IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000041>,
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<IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000040>,
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<IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000040>,
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<IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000040>,
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<IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000040>,
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<IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000040>,
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<IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000040>,
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<IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000040>,
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<IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000040>,
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<IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000040>,
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<IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000040>,
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<IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000040>,
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<IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000040>;
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};
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pinctrl_fec2: fec2grp {
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fsl,pins = <IMX8QXP_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x00000040>,
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<IMX8QXP_ESAI0_FSR_CONN_ENET1_RGMII_TXC 0x00000040>,
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<IMX8QXP_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x00000040>,
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<IMX8QXP_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x00000040>,
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<IMX8QXP_ESAI0_FST_CONN_ENET1_RGMII_TXD2 0x00000040>,
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<IMX8QXP_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 0x00000040>,
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<IMX8QXP_ESAI0_TX0_CONN_ENET1_RGMII_RXC 0x00000040>,
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<IMX8QXP_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x00000040>,
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<IMX8QXP_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x00000040>,
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<IMX8QXP_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x00000040>,
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<IMX8QXP_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 0x00000040>,
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<IMX8QXP_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 0x00000040>;
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};
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pinctrl_gpiobuttons: gpiobuttonsgrp {
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fsl,pins = <IMX8QXP_ADC_IN5_LSIO_GPIO1_IO13 0x00000020>,
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|
<IMX8QXP_ADC_IN4_LSIO_GPIO1_IO14 0x00000020>;
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|
};
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|
|
|
pinctrl_lpi2c2: lpi2c2grp {
|
|
fsl,pins = <IMX8QXP_MIPI_DSI1_GPIO0_00_ADMA_I2C2_SCL 0x06000021>,
|
|
<IMX8QXP_MIPI_DSI1_GPIO0_01_ADMA_I2C2_SDA 0x06000021>;
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|
};
|
|
|
|
pinctrl_lpi2c2gpio: lpi2c2gpiogrp {
|
|
fsl,pins = <IMX8QXP_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO31 0x06000021>,
|
|
<IMX8QXP_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 0x06000021>;
|
|
};
|
|
|
|
pinctrl_lpuart1: lpuart1grp {
|
|
fsl,pins = <IMX8QXP_UART1_RX_ADMA_UART1_RX 0x06000020>,
|
|
<IMX8QXP_UART1_TX_ADMA_UART1_TX 0x06000020>;
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|
};
|
|
|
|
pinctrl_lpuart3: lpuart3grp {
|
|
fsl,pins = <IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020>,
|
|
<IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020>;
|
|
};
|
|
|
|
pinctrl_lsgpio3: lsgpio3grp {
|
|
fsl,pins = <IMX8QXP_QSPI0A_SS1_B_LSIO_GPIO3_IO15 0x00000021>;
|
|
};
|
|
|
|
pinctrl_pca9538: pca9538grp {
|
|
fsl,pins = <IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x00000020>;
|
|
};
|
|
|
|
pinctrl_pcieb: pcieagrp {
|
|
fsl,pins = <IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000041>,
|
|
<IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x06000041>,
|
|
<IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000041>;
|
|
};
|
|
|
|
pinctrl_reg_pcie_1v5: regpcie1v5grp {
|
|
fsl,pins = <IMX8QXP_SAI1_RXC_LSIO_GPIO0_IO30 0x00000021>;
|
|
};
|
|
|
|
pinctrl_reg_pcie_3v3: regpcie3v3grp {
|
|
fsl,pins = <IMX8QXP_SAI1_RXFS_LSIO_GPIO0_IO31 0x00000021>;
|
|
};
|
|
|
|
pinctrl_sai1: sai1grp {
|
|
fsl,pins = <IMX8QXP_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 0x06000041>,
|
|
<IMX8QXP_FLEXCAN0_RX_ADMA_SAI1_TXC 0x06000041>,
|
|
<IMX8QXP_FLEXCAN0_TX_ADMA_SAI1_TXFS 0x06000041>,
|
|
<IMX8QXP_FLEXCAN1_RX_ADMA_SAI1_TXD 0x06000041>,
|
|
<IMX8QXP_FLEXCAN1_TX_ADMA_SAI1_RXD 0x06000041>;
|
|
};
|
|
|
|
pinctrl_spi1: spi1grp {
|
|
fsl,pins = <IMX8QXP_SAI0_TXC_ADMA_SPI1_SDI 0x00000041>,
|
|
<IMX8QXP_SAI0_TXD_ADMA_SPI1_SDO 0x00000041>,
|
|
<IMX8QXP_SAI0_TXFS_ADMA_SPI1_SCK 0x00000041>,
|
|
<IMX8QXP_SAI0_RXD_LSIO_GPIO0_IO27 0x00000021>,
|
|
<IMX8QXP_SAI1_RXD_LSIO_GPIO0_IO29 0x00000021>;
|
|
};
|
|
|
|
pinctrl_spi2: spi2grp {
|
|
fsl,pins = <IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK 0x00000041>,
|
|
<IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI 0x00000041>,
|
|
<IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO 0x00000041>,
|
|
<IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00 0x00000021>;
|
|
};
|
|
|
|
pinctrl_spi3: spi3grp {
|
|
fsl,pins = <IMX8QXP_SPI3_SCK_ADMA_SPI3_SCK 0x00000041>,
|
|
<IMX8QXP_SPI3_SDI_ADMA_SPI3_SDI 0x00000041>,
|
|
<IMX8QXP_SPI3_SDO_ADMA_SPI3_SDO 0x00000041>,
|
|
<IMX8QXP_SPI3_CS0_LSIO_GPIO0_IO16 0x00000021>,
|
|
<IMX8QXP_SPI3_CS1_ADMA_SPI3_CS1 0x00000021>;
|
|
};
|
|
|
|
pinctrl_usbotg1: usbotg1grp {
|
|
fsl,pins = <IMX8QXP_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021>,
|
|
<IMX8QXP_USB_SS3_TC2_CONN_USB_OTG1_OC 0x00000021>;
|
|
};
|
|
|
|
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
|
|
fsl,pins = <IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21 0x00000021>,
|
|
<IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22 0x00000021>;
|
|
};
|
|
|
|
pinctrl_usdhc2: usdhc2grp {
|
|
fsl,pins = <IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041>,
|
|
<IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021>,
|
|
<IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021>,
|
|
<IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021>,
|
|
<IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021>,
|
|
<IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021>,
|
|
<IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021>;
|
|
};
|
|
|
|
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
|
|
fsl,pins = <IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040>,
|
|
<IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020>,
|
|
<IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020>,
|
|
<IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020>,
|
|
<IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020>,
|
|
<IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020>,
|
|
<IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020>;
|
|
};
|
|
|
|
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
|
|
fsl,pins = <IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040>,
|
|
<IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020>,
|
|
<IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020>,
|
|
<IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020>,
|
|
<IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020>,
|
|
<IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020>,
|
|
<IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020>;
|
|
};
|
|
};
|