387 lines
9.8 KiB
Plaintext
387 lines
9.8 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
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/*
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* Samsung's Exynos 8895 SoC device tree source
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*
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* Copyright (c) 2024, Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
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*/
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#include <dt-bindings/clock/samsung,exynos8895.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "samsung,exynos8895";
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#address-cells = <2>;
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#size-cells = <1>;
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interrupt-parent = <&gic>;
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aliases {
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pinctrl0 = &pinctrl_alive;
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pinctrl1 = &pinctrl_abox;
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pinctrl2 = &pinctrl_vts;
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pinctrl3 = &pinctrl_fsys0;
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pinctrl4 = &pinctrl_fsys1;
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pinctrl5 = &pinctrl_busc;
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pinctrl6 = &pinctrl_peric0;
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pinctrl7 = &pinctrl_peric1;
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};
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arm-a53-pmu {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>,
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<&cpu1>,
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<&cpu2>,
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<&cpu3>;
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};
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/* There's no PMU model for the Mongoose cores */
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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core2 {
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cpu = <&cpu2>;
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};
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core3 {
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cpu = <&cpu3>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&cpu4>;
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};
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core1 {
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cpu = <&cpu5>;
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};
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core2 {
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cpu = <&cpu6>;
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};
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core3 {
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cpu = <&cpu7>;
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};
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};
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};
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cpu4: cpu@0 {
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device_type = "cpu";
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compatible = "samsung,mongoose-m2";
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reg = <0x0>;
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enable-method = "psci";
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};
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cpu5: cpu@1 {
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device_type = "cpu";
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compatible = "samsung,mongoose-m2";
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reg = <0x1>;
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enable-method = "psci";
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};
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cpu6: cpu@2 {
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device_type = "cpu";
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compatible = "samsung,mongoose-m2";
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reg = <0x2>;
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enable-method = "psci";
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};
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cpu7: cpu@3 {
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device_type = "cpu";
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compatible = "samsung,mongoose-m2";
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reg = <0x3>;
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enable-method = "psci";
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};
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cpu0: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x100>;
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enable-method = "psci";
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};
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cpu1: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x101>;
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enable-method = "psci";
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};
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cpu2: cpu@102 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x102>;
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enable-method = "psci";
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};
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cpu3: cpu@103 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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reg = <0x103>;
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enable-method = "psci";
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};
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};
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oscclk: osc-clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-output-names = "oscclk";
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};
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psci {
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compatible = "arm,psci";
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method = "smc";
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cpu_off = <0x84000002>;
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cpu_on = <0xc4000003>;
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cpu_suspend = <0xc4000001>;
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};
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soc: soc@0 {
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compatible = "simple-bus";
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ranges = <0x0 0x0 0x0 0x20000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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chipid@10000000 {
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compatible = "samsung,exynos8895-chipid",
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"samsung,exynos850-chipid";
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reg = <0x10000000 0x24>;
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};
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cmu_peris: clock-controller@10010000 {
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compatible = "samsung,exynos8895-cmu-peris";
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reg = <0x10010000 0x8000>;
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#clock-cells = <1>;
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clocks = <&oscclk>,
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<&cmu_top CLK_DOUT_CMU_PERIS_BUS>;
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clock-names = "oscclk", "bus";
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};
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timer@10040000 {
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compatible = "samsung,exynos8895-mct",
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"samsung,exynos4210-mct";
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reg = <0x10040000 0x800>;
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clocks = <&oscclk>, <&cmu_peris CLK_GOUT_PERIS_MCT_PCLK>;
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clock-names = "fin_pll", "mct";
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interrupts = <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
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};
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gic: interrupt-controller@10201000 {
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compatible = "arm,gic-400";
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reg = <0x10201000 0x1000>,
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<0x10202000 0x1000>,
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<0x10204000 0x2000>,
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<0x10206000 0x2000>;
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#interrupt-cells = <3>;
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interrupt-controller;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
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IRQ_TYPE_LEVEL_HIGH)>;
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#address-cells = <0>;
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#size-cells = <1>;
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};
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cmu_peric0: clock-controller@10400000 {
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compatible = "samsung,exynos8895-cmu-peric0";
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reg = <0x10400000 0x8000>;
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#clock-cells = <1>;
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clocks = <&oscclk>,
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<&cmu_top CLK_DOUT_CMU_PERIC0_BUS>,
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<&cmu_top CLK_DOUT_CMU_PERIC0_UART_DBG>,
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<&cmu_top CLK_DOUT_CMU_PERIC0_USI00>,
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<&cmu_top CLK_DOUT_CMU_PERIC0_USI01>,
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<&cmu_top CLK_DOUT_CMU_PERIC0_USI02>,
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<&cmu_top CLK_DOUT_CMU_PERIC0_USI03>;
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clock-names = "oscclk", "bus", "uart", "usi0",
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"usi1", "usi2", "usi3";
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};
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pinctrl_peric0: pinctrl@104d0000 {
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compatible = "samsung,exynos8895-pinctrl";
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reg = <0x104d0000 0x1000>;
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interrupts = <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>;
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};
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cmu_peric1: clock-controller@10800000 {
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compatible = "samsung,exynos8895-cmu-peric1";
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reg = <0x10800000 0x8000>;
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#clock-cells = <1>;
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clocks = <&oscclk>,
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<&cmu_top CLK_DOUT_CMU_PERIC1_BUS>,
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<&cmu_top CLK_DOUT_CMU_PERIC1_SPEEDY2>,
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<&cmu_top CLK_DOUT_CMU_PERIC1_SPI_CAM0>,
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<&cmu_top CLK_DOUT_CMU_PERIC1_SPI_CAM1>,
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<&cmu_top CLK_DOUT_CMU_PERIC1_UART_BT>,
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<&cmu_top CLK_DOUT_CMU_PERIC1_USI04>,
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<&cmu_top CLK_DOUT_CMU_PERIC1_USI05>,
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<&cmu_top CLK_DOUT_CMU_PERIC1_USI06>,
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<&cmu_top CLK_DOUT_CMU_PERIC1_USI07>,
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<&cmu_top CLK_DOUT_CMU_PERIC1_USI08>,
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<&cmu_top CLK_DOUT_CMU_PERIC1_USI09>,
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<&cmu_top CLK_DOUT_CMU_PERIC1_USI10>,
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<&cmu_top CLK_DOUT_CMU_PERIC1_USI11>,
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<&cmu_top CLK_DOUT_CMU_PERIC1_USI12>,
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<&cmu_top CLK_DOUT_CMU_PERIC1_USI13>;
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clock-names = "oscclk", "bus", "speedy", "cam0",
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"cam1", "uart", "usi4", "usi5",
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"usi6", "usi7", "usi8", "usi9",
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"usi10", "usi11", "usi12", "usi13";
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};
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pinctrl_peric1: pinctrl@10980000 {
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compatible = "samsung,exynos8895-pinctrl";
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reg = <0x10980000 0x1000>;
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interrupts = <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
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};
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spi_0: spi@109d0000 {
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compatible = "samsung,exynos8895-spi",
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"samsung,exynos850-spi";
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reg = <0x109d0000 0x100>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&cmu_peric1 CLK_GOUT_PERIC1_SPI_CAM0_PCLK>,
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<&cmu_peric1 CLK_GOUT_PERIC1_SPI_CAM0_SPI_EXT_CLK>;
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clock-names = "spi", "spi_busclk0";
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interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-0 = <&spi0_bus>;
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pinctrl-names = "default";
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status = "disabled";
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};
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spi_1: spi@109e0000 {
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compatible = "samsung,exynos8895-spi",
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"samsung,exynos850-spi";
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reg = <0x109e0000 0x100>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&cmu_peric1 CLK_GOUT_PERIC1_SPI_CAM1_PCLK>,
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<&cmu_peric1 CLK_GOUT_PERIC1_SPI_CAM1_SPI_EXT_CLK>;
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clock-names = "spi", "spi_busclk0";
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interrupts = <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-0 = <&spi1_bus>;
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pinctrl-names = "default";
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status = "disabled";
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};
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cmu_fsys0: clock-controller@11000000 {
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compatible = "samsung,exynos8895-cmu-fsys0";
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reg = <0x11000000 0x8000>;
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#clock-cells = <1>;
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clocks = <&oscclk>,
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<&cmu_top CLK_DOUT_CMU_FSYS0_BUS>,
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<&cmu_top CLK_DOUT_CMU_FSYS0_DPGTC>,
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<&cmu_top CLK_DOUT_CMU_FSYS0_MMC_EMBD>,
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<&cmu_top CLK_DOUT_CMU_FSYS0_UFS_EMBD>,
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<&cmu_top CLK_DOUT_CMU_FSYS0_USBDRD30>;
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clock-names = "oscclk", "bus", "dpgtc", "mmc",
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"ufs", "usbdrd30";
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};
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pinctrl_fsys0: pinctrl@11050000 {
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compatible = "samsung,exynos8895-pinctrl";
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reg = <0x11050000 0x1000>;
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interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
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};
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cmu_fsys1: clock-controller@11400000 {
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compatible = "samsung,exynos8895-cmu-fsys1";
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reg = <0x11400000 0x8000>;
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#clock-cells = <1>;
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clocks = <&oscclk>,
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<&cmu_top CLK_DOUT_CMU_FSYS1_BUS>,
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<&cmu_top CLK_DOUT_CMU_FSYS1_PCIE>,
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<&cmu_top CLK_DOUT_CMU_FSYS1_UFS_CARD>,
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<&cmu_top CLK_DOUT_CMU_FSYS1_MMC_CARD>;
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clock-names = "oscclk", "bus", "pcie", "ufs", "mmc";
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};
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pinctrl_fsys1: pinctrl@11430000 {
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compatible = "samsung,exynos8895-pinctrl";
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reg = <0x11430000 0x1000>;
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interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
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};
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pinctrl_abox: pinctrl@13e60000 {
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compatible = "samsung,exynos8895-pinctrl";
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reg = <0x13e60000 0x1000>;
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};
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pinctrl_vts: pinctrl@14080000 {
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compatible = "samsung,exynos8895-pinctrl";
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reg = <0x14080000 0x1000>;
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};
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pinctrl_busc: pinctrl@15a30000 {
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compatible = "samsung,exynos8895-pinctrl";
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reg = <0x15a30000 0x1000>;
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interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
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};
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cmu_top: clock-controller@15a80000 {
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compatible = "samsung,exynos8895-cmu-top";
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reg = <0x15a80000 0x8000>;
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#clock-cells = <1>;
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clocks = <&oscclk>;
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clock-names = "oscclk";
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};
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pmu_system_controller: system-controller@16480000 {
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compatible = "samsung,exynos8895-pmu",
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"samsung,exynos7-pmu", "syscon";
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reg = <0x16480000 0x10000>;
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};
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pinctrl_alive: pinctrl@164b0000 {
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compatible = "samsung,exynos8895-pinctrl";
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reg = <0x164b0000 0x1000>;
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wakeup-interrupt-controller {
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compatible = "samsung,exynos8895-wakeup-eint",
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"samsung,exynos7-wakeup-eint";
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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/* Hypervisor Virtual Timer interrupt is not wired to GIC */
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
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/*
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* Non-updatable, broken stock Samsung bootloader does not
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* configure CNTFRQ_EL0
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*/
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clock-frequency = <26000000>;
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};
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};
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#include "exynos8895-pinctrl.dtsi"
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#include "arm/samsung/exynos-syscon-restart.dtsi"
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