185 lines
4.7 KiB
YAML
185 lines
4.7 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/atmel,at91rm9200-pinctrl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Microchip PIO3 Pinmux Controller
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maintainers:
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- Manikandan Muralidharan <manikandan.m@microchip.com>
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description:
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The AT91 Pinmux Controller, enables the IC to share one PAD to several
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functional blocks. The sharing is done by multiplexing the PAD input/output
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signals. For each PAD there are up to 8 muxing options (called periph modes).
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Since different modules require different PAD settings (like pull up, keeper,
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etc) the controller controls also the PAD settings parameters.
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properties:
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compatible:
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oneOf:
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- items:
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- enum:
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- atmel,at91rm9200-pinctrl
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- atmel,at91sam9x5-pinctrl
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- atmel,sama5d3-pinctrl
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- microchip,sam9x60-pinctrl
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- const: simple-mfd
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- items:
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- enum:
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- microchip,sam9x7-pinctrl
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- const: microchip,sam9x60-pinctrl
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- const: simple-mfd
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'#address-cells':
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const: 1
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'#size-cells':
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const: 1
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ranges: true
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atmel,mux-mask:
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$ref: /schemas/types.yaml#/definitions/uint32-matrix
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description: |
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Array of mask (periph per bank) to describe if a pin can be
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configured in this periph mode. All the periph and bank need to
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be described.
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#How to create such array:
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Each column will represent the possible peripheral of the pinctrl
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Each line will represent a pio bank
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#Example:
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In at91sam9260.dtsi,
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Peripheral: 2 ( A and B)
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Bank: 3 (A, B and C)
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# A B
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0xffffffff 0xffc00c3b # pioA
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0xffffffff 0x7fff3ccf # pioB
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0xffffffff 0x007fffff # pioC
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For each peripheral/bank we will describe in a u32 if a pin can be
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configured in it by putting 1 to the pin bit (1 << pin)
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Let's take the pioA on peripheral B whose value is 0xffc00c3b
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From the datasheet Table 10-2.
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Peripheral B
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PA0 MCDB0
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PA1 MCCDB
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PA2
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PA3 MCDB3
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PA4 MCDB2
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PA5 MCDB1
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PA6
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PA7
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PA8
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PA9
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PA10 ETX2
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PA11 ETX3
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PA12
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PA13
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PA14
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PA15
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PA16
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PA17
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PA18
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PA19
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PA20
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PA21
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PA22 ETXER
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PA23 ETX2
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PA24 ETX3
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PA25 ERX2
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PA26 ERX3
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PA27 ERXCK
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PA28 ECRS
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PA29 ECOL
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PA30 RXD4
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PA31 TXD4
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allOf:
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- $ref: pinctrl.yaml#
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required:
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- compatible
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- ranges
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- "#address-cells"
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- "#size-cells"
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- atmel,mux-mask
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patternProperties:
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'gpio@[0-9a-f]+$':
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$ref: /schemas/gpio/atmel,at91rm9200-gpio.yaml
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unevaluatedProperties: false
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additionalProperties:
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type: object
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additionalProperties:
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type: object
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additionalProperties: false
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properties:
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atmel,pins:
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$ref: /schemas/types.yaml#/definitions/uint32-matrix
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description: |
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Each entry consists of 4 integers and represents the pins
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mux and config setting.The format is
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atmel,pins = <PIN_BANK PIN_BANK_NUM PERIPH CONFIG>.
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Supported pin number and mux varies for different SoCs, and
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are defined in <include/dt-bindings/pinctrl/at91.h>.
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items:
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items:
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- description:
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Pin bank
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- description:
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Pin bank index
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- description:
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Peripheral function
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- description:
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Pad configuration
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examples:
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- |
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#include <dt-bindings/clock/at91.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/pinctrl/at91.h>
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pinctrl@fffff400 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "atmel,at91rm9200-pinctrl", "simple-mfd";
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ranges = <0xfffff400 0xfffff400 0x600>;
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atmel,mux-mask = <
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/* A B */
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0xffffffff 0xffc00c3b /* pioA */
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0xffffffff 0x7fff3ccf /* pioB */
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0xffffffff 0x007fffff /* pioC */
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>;
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dbgu {
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pinctrl_dbgu: dbgu-0 {
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atmel,pins =
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<AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_PULL_UP
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AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
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};
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};
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pioA: gpio@fffff400 {
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compatible = "atmel,at91rm9200-gpio";
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reg = <0xfffff400 0x200>;
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interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
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#gpio-cells = <2>;
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gpio-controller;
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interrupt-controller;
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#interrupt-cells = <2>;
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clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
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};
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};
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...
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