81 lines
1.9 KiB
YAML
81 lines
1.9 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/phy/mediatek,mt7988-xfi-tphy.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek MT7988 XFI T-PHY
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maintainers:
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- Daniel Golle <daniel@makrotopia.org>
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description:
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The MediaTek XFI SerDes T-PHY provides the physical SerDes lanes
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used by the (10G/5G) USXGMII PCS and (1G/2.5G) LynxI PCS found in
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MediaTek's 10G-capabale MT7988 SoC.
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In MediaTek's SDK sources, this unit is referred to as "pextp".
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properties:
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compatible:
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const: mediatek,mt7988-xfi-tphy
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reg:
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maxItems: 1
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clocks:
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items:
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- description: XFI PHY clock
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- description: XFI register clock
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clock-names:
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items:
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- const: xfipll
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- const: topxtal
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resets:
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items:
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- description: Reset controller corresponding to the phy instance.
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mediatek,usxgmii-performance-errata:
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$ref: /schemas/types.yaml#/definitions/flag
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description:
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One instance of the T-PHY on MT7988 suffers from a performance
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problem in 10GBase-R mode which needs a work-around in the driver.
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This flag enables a work-around adjusting an analog phy setting and
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is required for XFI Port0 of the MT7988 SoC to be in compliance with
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the SFP specification.
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"#phy-cells":
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const: 0
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- resets
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- "#phy-cells"
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/mediatek,mt7988-clk.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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phy@11f20000 {
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compatible = "mediatek,mt7988-xfi-tphy";
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reg = <0 0x11f20000 0 0x10000>;
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clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>,
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<&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>;
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clock-names = "xfipll", "topxtal";
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resets = <&watchdog 14>;
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mediatek,usxgmii-performance-errata;
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#phy-cells = <0>;
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};
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};
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...
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