137 lines
4.5 KiB
YAML
137 lines
4.5 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/pcs/snps,dw-xpcs.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Synopsys DesignWare Ethernet PCS
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maintainers:
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- Serge Semin <fancer.lancer@gmail.com>
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description:
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Synopsys DesignWare Ethernet Physical Coding Sublayer provides an interface
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between Media Access Control and Physical Medium Attachment Sublayer through
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the Media Independent Interface (XGMII, USXGMII, XLGMII, GMII, etc)
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controlled by means of the IEEE std. Clause 45 registers set. The PCS can be
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optionally synthesized with a vendor-specific interface connected to
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Synopsys PMA (also called DesignWare Consumer/Enterprise PHY) although in
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general it can be used to communicate with any compatible PHY.
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The PCS CSRs can be accessible either over the Ethernet MDIO bus or directly
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by means of the APB3/MCI interfaces. In the later case the XPCS can be mapped
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right to the system IO memory space.
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properties:
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compatible:
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oneOf:
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- description: Synopsys DesignWare XPCS with none or unknown PMA
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const: snps,dw-xpcs
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- description: Synopsys DesignWare XPCS with Consumer Gen1 3G PMA
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const: snps,dw-xpcs-gen1-3g
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- description: Synopsys DesignWare XPCS with Consumer Gen2 3G PMA
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const: snps,dw-xpcs-gen2-3g
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- description: Synopsys DesignWare XPCS with Consumer Gen2 6G PMA
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const: snps,dw-xpcs-gen2-6g
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- description: Synopsys DesignWare XPCS with Consumer Gen4 3G PMA
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const: snps,dw-xpcs-gen4-3g
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- description: Synopsys DesignWare XPCS with Consumer Gen4 6G PMA
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const: snps,dw-xpcs-gen4-6g
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- description: Synopsys DesignWare XPCS with Consumer Gen5 10G PMA
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const: snps,dw-xpcs-gen5-10g
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- description: Synopsys DesignWare XPCS with Consumer Gen5 12G PMA
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const: snps,dw-xpcs-gen5-12g
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reg:
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items:
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- description:
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In case of the MDIO management interface this just a 5-bits ID
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of the MDIO bus device. If DW XPCS CSRs space is accessed over the
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MCI or APB3 management interfaces, then the space mapping can be
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either 'direct' or 'indirect'. In the former case all Clause 45
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registers are contiguously mapped within the address space
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MMD '[20:16]', Reg '[15:0]'. In the later case the space is divided
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to the multiple 256 register sets. There is a special viewport CSR
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which is responsible for the set selection. The upper part of
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the CSR address MMD+REG[20:8] is supposed to be written in there
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so the corresponding subset would be mapped to the lowest 255 CSRs.
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reg-names:
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items:
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- enum: [ direct, indirect ]
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reg-io-width:
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description:
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The way the CSRs are mapped to the memory is platform depended. Since
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each Clause 45 CSR is of 16-bits wide the access instructions must be
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two bytes aligned at least.
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default: 2
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enum: [ 2, 4 ]
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interrupts:
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description:
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System interface interrupt output (sbd_intr_o) indicating Clause 73/37
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auto-negotiation events':' Page received, AN is completed or incompatible
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link partner.
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maxItems: 1
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clocks:
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description:
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The MCI and APB3 interfaces are supposed to be equipped with a clock
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source connected to the clk_csr_i line.
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PCS/PMA layer can be clocked by an internal reference clock source
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(phyN_core_refclk) or by an externally connected (phyN_pad_refclk) clock
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generator. Both clocks can be supplied at a time.
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minItems: 1
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maxItems: 3
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clock-names:
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oneOf:
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- minItems: 1
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items: # MDIO
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- enum: [core, pad]
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- const: pad
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- minItems: 1
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items: # MCI or APB
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- const: csr
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- enum: [core, pad]
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- const: pad
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required:
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- compatible
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- reg
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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ethernet-pcs@1f05d000 {
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compatible = "snps,dw-xpcs";
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reg = <0x1f05d000 0x1000>;
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reg-names = "indirect";
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reg-io-width = <4>;
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interrupts = <79 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu_pclk>, <&ccu_core>, <&ccu_pad>;
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clock-names = "csr", "core", "pad";
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};
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- |
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mdio-bus {
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#address-cells = <1>;
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#size-cells = <0>;
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ethernet-pcs@0 {
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compatible = "snps,dw-xpcs";
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reg = <0>;
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clocks = <&ccu_core>, <&ccu_pad>;
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clock-names = "core", "pad";
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};
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};
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...
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