599 lines
17 KiB
C
599 lines
17 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* x86 instruction nmemonic table to parse disasm lines for annotate.
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* This table is searched twice - one for exact match and another for
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* match without a size suffix (b, w, l, q) in case of AT&T syntax.
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*
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* So this table should not have entries with the suffix unless it's
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* a complete different instruction than ones without the suffix.
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*/
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static struct ins x86__instructions[] = {
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{ .name = "adc", .ops = &mov_ops, },
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{ .name = "add", .ops = &mov_ops, },
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{ .name = "addsd", .ops = &mov_ops, },
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{ .name = "and", .ops = &mov_ops, },
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{ .name = "andpd", .ops = &mov_ops, },
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{ .name = "andps", .ops = &mov_ops, },
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{ .name = "bsr", .ops = &mov_ops, },
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{ .name = "bt", .ops = &mov_ops, },
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{ .name = "btr", .ops = &mov_ops, },
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{ .name = "bts", .ops = &mov_ops, },
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{ .name = "call", .ops = &call_ops, },
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{ .name = "cmovbe", .ops = &mov_ops, },
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{ .name = "cmove", .ops = &mov_ops, },
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{ .name = "cmovae", .ops = &mov_ops, },
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{ .name = "cmp", .ops = &mov_ops, },
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{ .name = "cmpxch", .ops = &mov_ops, },
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{ .name = "cmpxchg", .ops = &mov_ops, },
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{ .name = "cs", .ops = &mov_ops, },
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{ .name = "dec", .ops = &dec_ops, },
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{ .name = "divsd", .ops = &mov_ops, },
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{ .name = "divss", .ops = &mov_ops, },
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{ .name = "gs", .ops = &mov_ops, },
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{ .name = "imul", .ops = &mov_ops, },
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{ .name = "inc", .ops = &dec_ops, },
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{ .name = "ja", .ops = &jump_ops, },
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{ .name = "jae", .ops = &jump_ops, },
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{ .name = "jb", .ops = &jump_ops, },
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{ .name = "jbe", .ops = &jump_ops, },
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{ .name = "jc", .ops = &jump_ops, },
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{ .name = "jcxz", .ops = &jump_ops, },
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{ .name = "je", .ops = &jump_ops, },
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{ .name = "jecxz", .ops = &jump_ops, },
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{ .name = "jg", .ops = &jump_ops, },
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{ .name = "jge", .ops = &jump_ops, },
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{ .name = "jl", .ops = &jump_ops, },
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{ .name = "jle", .ops = &jump_ops, },
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{ .name = "jmp", .ops = &jump_ops, },
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{ .name = "jna", .ops = &jump_ops, },
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{ .name = "jnae", .ops = &jump_ops, },
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{ .name = "jnb", .ops = &jump_ops, },
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{ .name = "jnbe", .ops = &jump_ops, },
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{ .name = "jnc", .ops = &jump_ops, },
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{ .name = "jne", .ops = &jump_ops, },
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{ .name = "jng", .ops = &jump_ops, },
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{ .name = "jnge", .ops = &jump_ops, },
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{ .name = "jnl", .ops = &jump_ops, },
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{ .name = "jnle", .ops = &jump_ops, },
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{ .name = "jno", .ops = &jump_ops, },
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{ .name = "jnp", .ops = &jump_ops, },
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{ .name = "jns", .ops = &jump_ops, },
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{ .name = "jnz", .ops = &jump_ops, },
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{ .name = "jo", .ops = &jump_ops, },
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{ .name = "jp", .ops = &jump_ops, },
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{ .name = "jpe", .ops = &jump_ops, },
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{ .name = "jpo", .ops = &jump_ops, },
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{ .name = "jrcxz", .ops = &jump_ops, },
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{ .name = "js", .ops = &jump_ops, },
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{ .name = "jz", .ops = &jump_ops, },
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{ .name = "lea", .ops = &mov_ops, },
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{ .name = "lock", .ops = &lock_ops, },
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{ .name = "mov", .ops = &mov_ops, },
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{ .name = "movapd", .ops = &mov_ops, },
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{ .name = "movaps", .ops = &mov_ops, },
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{ .name = "movdqa", .ops = &mov_ops, },
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{ .name = "movdqu", .ops = &mov_ops, },
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{ .name = "movsd", .ops = &mov_ops, },
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{ .name = "movss", .ops = &mov_ops, },
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{ .name = "movsb", .ops = &mov_ops, },
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{ .name = "movsw", .ops = &mov_ops, },
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{ .name = "movsl", .ops = &mov_ops, },
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{ .name = "movupd", .ops = &mov_ops, },
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{ .name = "movups", .ops = &mov_ops, },
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{ .name = "movzb", .ops = &mov_ops, },
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{ .name = "movzw", .ops = &mov_ops, },
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{ .name = "movzl", .ops = &mov_ops, },
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{ .name = "mulsd", .ops = &mov_ops, },
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{ .name = "mulss", .ops = &mov_ops, },
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{ .name = "nop", .ops = &nop_ops, },
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{ .name = "or", .ops = &mov_ops, },
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{ .name = "orps", .ops = &mov_ops, },
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{ .name = "pand", .ops = &mov_ops, },
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{ .name = "paddq", .ops = &mov_ops, },
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{ .name = "pcmpeqb", .ops = &mov_ops, },
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{ .name = "por", .ops = &mov_ops, },
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{ .name = "rcl", .ops = &mov_ops, },
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{ .name = "ret", .ops = &ret_ops, },
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{ .name = "sbb", .ops = &mov_ops, },
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{ .name = "sete", .ops = &mov_ops, },
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{ .name = "sub", .ops = &mov_ops, },
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{ .name = "subsd", .ops = &mov_ops, },
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{ .name = "test", .ops = &mov_ops, },
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{ .name = "tzcnt", .ops = &mov_ops, },
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{ .name = "ucomisd", .ops = &mov_ops, },
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{ .name = "ucomiss", .ops = &mov_ops, },
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{ .name = "vaddsd", .ops = &mov_ops, },
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{ .name = "vandpd", .ops = &mov_ops, },
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{ .name = "vmovdqa", .ops = &mov_ops, },
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{ .name = "vmovq", .ops = &mov_ops, },
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{ .name = "vmovsd", .ops = &mov_ops, },
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{ .name = "vmulsd", .ops = &mov_ops, },
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{ .name = "vorpd", .ops = &mov_ops, },
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{ .name = "vsubsd", .ops = &mov_ops, },
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{ .name = "vucomisd", .ops = &mov_ops, },
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{ .name = "xadd", .ops = &mov_ops, },
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{ .name = "xbegin", .ops = &jump_ops, },
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{ .name = "xchg", .ops = &mov_ops, },
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{ .name = "xor", .ops = &mov_ops, },
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{ .name = "xorpd", .ops = &mov_ops, },
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{ .name = "xorps", .ops = &mov_ops, },
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};
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static bool amd__ins_is_fused(struct arch *arch, const char *ins1,
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const char *ins2)
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{
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if (strstr(ins2, "jmp"))
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return false;
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/* Family >= 15h supports cmp/test + branch fusion */
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if (arch->family >= 0x15 && (strstarts(ins1, "test") ||
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(strstarts(ins1, "cmp") && !strstr(ins1, "xchg")))) {
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return true;
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}
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/* Family >= 19h supports some ALU + branch fusion */
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if (arch->family >= 0x19 && (strstarts(ins1, "add") ||
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strstarts(ins1, "sub") || strstarts(ins1, "and") ||
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strstarts(ins1, "inc") || strstarts(ins1, "dec") ||
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strstarts(ins1, "or") || strstarts(ins1, "xor"))) {
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return true;
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}
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return false;
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}
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static bool intel__ins_is_fused(struct arch *arch, const char *ins1,
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const char *ins2)
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{
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if (arch->family != 6 || arch->model < 0x1e || strstr(ins2, "jmp"))
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return false;
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if (arch->model == 0x1e) {
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/* Nehalem */
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if ((strstr(ins1, "cmp") && !strstr(ins1, "xchg")) ||
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strstr(ins1, "test")) {
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return true;
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}
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} else {
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/* Newer platform */
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if ((strstr(ins1, "cmp") && !strstr(ins1, "xchg")) ||
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strstr(ins1, "test") ||
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strstr(ins1, "add") ||
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strstr(ins1, "sub") ||
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strstr(ins1, "and") ||
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strstr(ins1, "inc") ||
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strstr(ins1, "dec")) {
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return true;
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}
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}
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return false;
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}
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static int x86__cpuid_parse(struct arch *arch, char *cpuid)
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{
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unsigned int family, model, stepping;
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int ret;
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/*
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* cpuid = "GenuineIntel,family,model,stepping"
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*/
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ret = sscanf(cpuid, "%*[^,],%u,%u,%u", &family, &model, &stepping);
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if (ret == 3) {
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arch->family = family;
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arch->model = model;
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arch->ins_is_fused = strstarts(cpuid, "AuthenticAMD") ?
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amd__ins_is_fused :
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intel__ins_is_fused;
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return 0;
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}
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return -1;
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}
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static int x86__annotate_init(struct arch *arch, char *cpuid)
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{
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int err = 0;
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if (arch->initialized)
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return 0;
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if (cpuid) {
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if (x86__cpuid_parse(arch, cpuid))
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err = SYMBOL_ANNOTATE_ERRNO__ARCH_INIT_CPUID_PARSING;
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}
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arch->e_machine = EM_X86_64;
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arch->e_flags = 0;
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arch->initialized = true;
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return err;
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}
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#ifdef HAVE_LIBDW_SUPPORT
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static void update_insn_state_x86(struct type_state *state,
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struct data_loc_info *dloc, Dwarf_Die *cu_die,
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struct disasm_line *dl)
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{
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struct annotated_insn_loc loc;
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struct annotated_op_loc *src = &loc.ops[INSN_OP_SOURCE];
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struct annotated_op_loc *dst = &loc.ops[INSN_OP_TARGET];
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struct type_state_reg *tsr;
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Dwarf_Die type_die;
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u32 insn_offset = dl->al.offset;
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int fbreg = dloc->fbreg;
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int fboff = 0;
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if (annotate_get_insn_location(dloc->arch, dl, &loc) < 0)
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return;
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if (ins__is_call(&dl->ins)) {
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struct symbol *func = dl->ops.target.sym;
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if (func == NULL)
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return;
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/* __fentry__ will preserve all registers */
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if (!strcmp(func->name, "__fentry__"))
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return;
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pr_debug_dtp("call [%x] %s\n", insn_offset, func->name);
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/* Otherwise invalidate caller-saved registers after call */
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for (unsigned i = 0; i < ARRAY_SIZE(state->regs); i++) {
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if (state->regs[i].caller_saved)
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state->regs[i].ok = false;
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}
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/* Update register with the return type (if any) */
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if (die_find_func_rettype(cu_die, func->name, &type_die)) {
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tsr = &state->regs[state->ret_reg];
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tsr->type = type_die;
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tsr->kind = TSR_KIND_TYPE;
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tsr->ok = true;
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pr_debug_dtp("call [%x] return -> reg%d",
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insn_offset, state->ret_reg);
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pr_debug_type_name(&type_die, tsr->kind);
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}
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return;
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}
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if (!strncmp(dl->ins.name, "add", 3)) {
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u64 imm_value = -1ULL;
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int offset;
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const char *var_name = NULL;
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struct map_symbol *ms = dloc->ms;
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u64 ip = ms->sym->start + dl->al.offset;
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if (!has_reg_type(state, dst->reg1))
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return;
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tsr = &state->regs[dst->reg1];
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tsr->copied_from = -1;
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if (src->imm)
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imm_value = src->offset;
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else if (has_reg_type(state, src->reg1) &&
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state->regs[src->reg1].kind == TSR_KIND_CONST)
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imm_value = state->regs[src->reg1].imm_value;
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else if (src->reg1 == DWARF_REG_PC) {
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u64 var_addr = annotate_calc_pcrel(dloc->ms, ip,
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src->offset, dl);
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if (get_global_var_info(dloc, var_addr,
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&var_name, &offset) &&
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!strcmp(var_name, "this_cpu_off") &&
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tsr->kind == TSR_KIND_CONST) {
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tsr->kind = TSR_KIND_PERCPU_BASE;
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tsr->ok = true;
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imm_value = tsr->imm_value;
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}
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}
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else
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return;
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if (tsr->kind != TSR_KIND_PERCPU_BASE)
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return;
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if (get_global_var_type(cu_die, dloc, ip, imm_value, &offset,
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&type_die) && offset == 0) {
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/*
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* This is not a pointer type, but it should be treated
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* as a pointer.
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*/
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tsr->type = type_die;
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tsr->kind = TSR_KIND_POINTER;
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tsr->ok = true;
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pr_debug_dtp("add [%x] percpu %#"PRIx64" -> reg%d",
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insn_offset, imm_value, dst->reg1);
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pr_debug_type_name(&tsr->type, tsr->kind);
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}
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return;
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}
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if (strncmp(dl->ins.name, "mov", 3))
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return;
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if (dloc->fb_cfa) {
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u64 ip = dloc->ms->sym->start + dl->al.offset;
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u64 pc = map__rip_2objdump(dloc->ms->map, ip);
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if (die_get_cfa(dloc->di->dbg, pc, &fbreg, &fboff) < 0)
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fbreg = -1;
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}
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/* Case 1. register to register or segment:offset to register transfers */
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if (!src->mem_ref && !dst->mem_ref) {
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if (!has_reg_type(state, dst->reg1))
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return;
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tsr = &state->regs[dst->reg1];
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tsr->copied_from = -1;
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if (dso__kernel(map__dso(dloc->ms->map)) &&
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src->segment == INSN_SEG_X86_GS && src->imm) {
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u64 ip = dloc->ms->sym->start + dl->al.offset;
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u64 var_addr;
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int offset;
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/*
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* In kernel, %gs points to a per-cpu region for the
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* current CPU. Access with a constant offset should
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* be treated as a global variable access.
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*/
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var_addr = src->offset;
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if (var_addr == 40) {
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tsr->kind = TSR_KIND_CANARY;
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tsr->ok = true;
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pr_debug_dtp("mov [%x] stack canary -> reg%d\n",
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insn_offset, dst->reg1);
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return;
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}
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if (!get_global_var_type(cu_die, dloc, ip, var_addr,
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&offset, &type_die) ||
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!die_get_member_type(&type_die, offset, &type_die)) {
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tsr->ok = false;
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return;
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}
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tsr->type = type_die;
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tsr->kind = TSR_KIND_TYPE;
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tsr->ok = true;
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pr_debug_dtp("mov [%x] this-cpu addr=%#"PRIx64" -> reg%d",
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insn_offset, var_addr, dst->reg1);
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pr_debug_type_name(&tsr->type, tsr->kind);
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return;
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}
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if (src->imm) {
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tsr->kind = TSR_KIND_CONST;
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tsr->imm_value = src->offset;
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tsr->ok = true;
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pr_debug_dtp("mov [%x] imm=%#x -> reg%d\n",
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insn_offset, tsr->imm_value, dst->reg1);
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return;
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}
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if (!has_reg_type(state, src->reg1) ||
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!state->regs[src->reg1].ok) {
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tsr->ok = false;
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return;
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}
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tsr->type = state->regs[src->reg1].type;
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tsr->kind = state->regs[src->reg1].kind;
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tsr->imm_value = state->regs[src->reg1].imm_value;
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tsr->ok = true;
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/* To copy back the variable type later (hopefully) */
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if (tsr->kind == TSR_KIND_TYPE)
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tsr->copied_from = src->reg1;
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pr_debug_dtp("mov [%x] reg%d -> reg%d",
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insn_offset, src->reg1, dst->reg1);
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pr_debug_type_name(&tsr->type, tsr->kind);
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}
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/* Case 2. memory to register transers */
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if (src->mem_ref && !dst->mem_ref) {
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int sreg = src->reg1;
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if (!has_reg_type(state, dst->reg1))
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return;
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tsr = &state->regs[dst->reg1];
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tsr->copied_from = -1;
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retry:
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/* Check stack variables with offset */
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if (sreg == fbreg) {
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struct type_state_stack *stack;
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int offset = src->offset - fboff;
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stack = find_stack_state(state, offset);
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if (stack == NULL) {
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tsr->ok = false;
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return;
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} else if (!stack->compound) {
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tsr->type = stack->type;
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tsr->kind = stack->kind;
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tsr->ok = true;
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} else if (die_get_member_type(&stack->type,
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offset - stack->offset,
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&type_die)) {
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tsr->type = type_die;
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tsr->kind = TSR_KIND_TYPE;
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tsr->ok = true;
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} else {
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tsr->ok = false;
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return;
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}
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pr_debug_dtp("mov [%x] -%#x(stack) -> reg%d",
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insn_offset, -offset, dst->reg1);
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pr_debug_type_name(&tsr->type, tsr->kind);
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}
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/* And then dereference the pointer if it has one */
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else if (has_reg_type(state, sreg) && state->regs[sreg].ok &&
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state->regs[sreg].kind == TSR_KIND_TYPE &&
|
|
die_deref_ptr_type(&state->regs[sreg].type,
|
|
src->offset, &type_die)) {
|
|
tsr->type = type_die;
|
|
tsr->kind = TSR_KIND_TYPE;
|
|
tsr->ok = true;
|
|
|
|
pr_debug_dtp("mov [%x] %#x(reg%d) -> reg%d",
|
|
insn_offset, src->offset, sreg, dst->reg1);
|
|
pr_debug_type_name(&tsr->type, tsr->kind);
|
|
}
|
|
/* Or check if it's a global variable */
|
|
else if (sreg == DWARF_REG_PC) {
|
|
struct map_symbol *ms = dloc->ms;
|
|
u64 ip = ms->sym->start + dl->al.offset;
|
|
u64 addr;
|
|
int offset;
|
|
|
|
addr = annotate_calc_pcrel(ms, ip, src->offset, dl);
|
|
|
|
if (!get_global_var_type(cu_die, dloc, ip, addr, &offset,
|
|
&type_die) ||
|
|
!die_get_member_type(&type_die, offset, &type_die)) {
|
|
tsr->ok = false;
|
|
return;
|
|
}
|
|
|
|
tsr->type = type_die;
|
|
tsr->kind = TSR_KIND_TYPE;
|
|
tsr->ok = true;
|
|
|
|
pr_debug_dtp("mov [%x] global addr=%"PRIx64" -> reg%d",
|
|
insn_offset, addr, dst->reg1);
|
|
pr_debug_type_name(&type_die, tsr->kind);
|
|
}
|
|
/* And check percpu access with base register */
|
|
else if (has_reg_type(state, sreg) &&
|
|
state->regs[sreg].kind == TSR_KIND_PERCPU_BASE) {
|
|
u64 ip = dloc->ms->sym->start + dl->al.offset;
|
|
u64 var_addr = src->offset;
|
|
int offset;
|
|
|
|
if (src->multi_regs) {
|
|
int reg2 = (sreg == src->reg1) ? src->reg2 : src->reg1;
|
|
|
|
if (has_reg_type(state, reg2) && state->regs[reg2].ok &&
|
|
state->regs[reg2].kind == TSR_KIND_CONST)
|
|
var_addr += state->regs[reg2].imm_value;
|
|
}
|
|
|
|
/*
|
|
* In kernel, %gs points to a per-cpu region for the
|
|
* current CPU. Access with a constant offset should
|
|
* be treated as a global variable access.
|
|
*/
|
|
if (get_global_var_type(cu_die, dloc, ip, var_addr,
|
|
&offset, &type_die) &&
|
|
die_get_member_type(&type_die, offset, &type_die)) {
|
|
tsr->type = type_die;
|
|
tsr->kind = TSR_KIND_TYPE;
|
|
tsr->ok = true;
|
|
|
|
if (src->multi_regs) {
|
|
pr_debug_dtp("mov [%x] percpu %#x(reg%d,reg%d) -> reg%d",
|
|
insn_offset, src->offset, src->reg1,
|
|
src->reg2, dst->reg1);
|
|
} else {
|
|
pr_debug_dtp("mov [%x] percpu %#x(reg%d) -> reg%d",
|
|
insn_offset, src->offset, sreg, dst->reg1);
|
|
}
|
|
pr_debug_type_name(&tsr->type, tsr->kind);
|
|
} else {
|
|
tsr->ok = false;
|
|
}
|
|
}
|
|
/* And then dereference the calculated pointer if it has one */
|
|
else if (has_reg_type(state, sreg) && state->regs[sreg].ok &&
|
|
state->regs[sreg].kind == TSR_KIND_POINTER &&
|
|
die_get_member_type(&state->regs[sreg].type,
|
|
src->offset, &type_die)) {
|
|
tsr->type = type_die;
|
|
tsr->kind = TSR_KIND_TYPE;
|
|
tsr->ok = true;
|
|
|
|
pr_debug_dtp("mov [%x] pointer %#x(reg%d) -> reg%d",
|
|
insn_offset, src->offset, sreg, dst->reg1);
|
|
pr_debug_type_name(&tsr->type, tsr->kind);
|
|
}
|
|
/* Or try another register if any */
|
|
else if (src->multi_regs && sreg == src->reg1 &&
|
|
src->reg1 != src->reg2) {
|
|
sreg = src->reg2;
|
|
goto retry;
|
|
}
|
|
else {
|
|
int offset;
|
|
const char *var_name = NULL;
|
|
|
|
/* it might be per-cpu variable (in kernel) access */
|
|
if (src->offset < 0) {
|
|
if (get_global_var_info(dloc, (s64)src->offset,
|
|
&var_name, &offset) &&
|
|
!strcmp(var_name, "__per_cpu_offset")) {
|
|
tsr->kind = TSR_KIND_PERCPU_BASE;
|
|
tsr->ok = true;
|
|
|
|
pr_debug_dtp("mov [%x] percpu base reg%d\n",
|
|
insn_offset, dst->reg1);
|
|
return;
|
|
}
|
|
}
|
|
|
|
tsr->ok = false;
|
|
}
|
|
}
|
|
/* Case 3. register to memory transfers */
|
|
if (!src->mem_ref && dst->mem_ref) {
|
|
if (!has_reg_type(state, src->reg1) ||
|
|
!state->regs[src->reg1].ok)
|
|
return;
|
|
|
|
/* Check stack variables with offset */
|
|
if (dst->reg1 == fbreg) {
|
|
struct type_state_stack *stack;
|
|
int offset = dst->offset - fboff;
|
|
|
|
tsr = &state->regs[src->reg1];
|
|
|
|
stack = find_stack_state(state, offset);
|
|
if (stack) {
|
|
/*
|
|
* The source register is likely to hold a type
|
|
* of member if it's a compound type. Do not
|
|
* update the stack variable type since we can
|
|
* get the member type later by using the
|
|
* die_get_member_type().
|
|
*/
|
|
if (!stack->compound)
|
|
set_stack_state(stack, offset, tsr->kind,
|
|
&tsr->type);
|
|
} else {
|
|
findnew_stack_state(state, offset, tsr->kind,
|
|
&tsr->type);
|
|
}
|
|
|
|
pr_debug_dtp("mov [%x] reg%d -> -%#x(stack)",
|
|
insn_offset, src->reg1, -offset);
|
|
pr_debug_type_name(&tsr->type, tsr->kind);
|
|
}
|
|
/*
|
|
* Ignore other transfers since it'd set a value in a struct
|
|
* and won't change the type.
|
|
*/
|
|
}
|
|
/* Case 4. memory to memory transfers (not handled for now) */
|
|
}
|
|
#endif
|