148 lines
5.6 KiB
C
148 lines
5.6 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
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/*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* Copyright(c) 2020-2022 Intel Corporation
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*/
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/* DSP Registers */
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#define MTL_HFDSSCS 0x1000
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#define MTL_HFDSSCS_SPA_MASK BIT(16)
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#define MTL_HFDSSCS_CPA_MASK BIT(24)
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#define MTL_HFSNDWIE 0x114C
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#define MTL_HFPWRCTL 0x1D18
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#define PTL_HFPWRCTL2 0x1D20
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#define MTL_HfPWRCTL_WPIOXPG(x) BIT((x) + 8)
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#define MTL_HFPWRCTL_WPDSPHPXPG BIT(0)
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#define MTL_HFPWRSTS 0x1D1C
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#define PTL_HFPWRSTS2 0x1D24
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#define MTL_HFPWRSTS_DSPHPXPGS_MASK BIT(0)
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#define MTL_HFINTIPPTR 0x1108
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#define MTL_IRQ_INTEN_L_HOST_IPC_MASK BIT(0)
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#define MTL_IRQ_INTEN_L_SOUNDWIRE_MASK BIT(6)
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#define MTL_HFINTIPPTR_PTR_MASK GENMASK(20, 0)
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#define MTL_HDA_VS_D0I3C 0x1D4A
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#define MTL_DSP2CXCAP_PRIMARY_CORE 0x178D00
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#define MTL_DSP2CXCTL_PRIMARY_CORE 0x178D04
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#define MTL_DSP2CXCTL_PRIMARY_CORE_SPA_MASK BIT(0)
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#define MTL_DSP2CXCTL_PRIMARY_CORE_CPA_MASK BIT(8)
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#define MTL_DSP2CXCTL_PRIMARY_CORE_OSEL GENMASK(25, 24)
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#define MTL_DSP2CXCTL_PRIMARY_CORE_OSEL_SHIFT 24
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/* IPC Registers */
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#define MTL_DSP_REG_HFIPCXTDR 0x73200
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#define MTL_DSP_REG_HFIPCXTDR_BUSY BIT(31)
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#define MTL_DSP_REG_HFIPCXTDR_MSG_MASK GENMASK(30, 0)
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#define MTL_DSP_REG_HFIPCXTDA 0x73204
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#define MTL_DSP_REG_HFIPCXTDA_BUSY BIT(31)
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#define MTL_DSP_REG_HFIPCXIDR 0x73210
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#define MTL_DSP_REG_HFIPCXIDR_BUSY BIT(31)
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#define MTL_DSP_REG_HFIPCXIDR_MSG_MASK GENMASK(30, 0)
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#define MTL_DSP_REG_HFIPCXIDA 0x73214
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#define MTL_DSP_REG_HFIPCXIDA_DONE BIT(31)
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#define MTL_DSP_REG_HFIPCXIDA_MSG_MASK GENMASK(30, 0)
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#define MTL_DSP_REG_HFIPCXCTL 0x73228
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#define MTL_DSP_REG_HFIPCXCTL_BUSY BIT(0)
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#define MTL_DSP_REG_HFIPCXCTL_DONE BIT(1)
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#define MTL_DSP_REG_HFIPCXTDDY 0x73300
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#define MTL_DSP_REG_HFIPCXIDDY 0x73380
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#define MTL_DSP_REG_HfHIPCIE 0x1140
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#define MTL_DSP_REG_HfHIPCIE_IE_MASK BIT(0)
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#define MTL_DSP_REG_HfSNDWIE 0x114C
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#define MTL_DSP_REG_HfSNDWIE_IE_MASK GENMASK(3, 0)
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#define MTL_DSP_IRQSTS 0x20
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#define MTL_DSP_IRQSTS_IPC BIT(0)
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#define MTL_DSP_IRQSTS_SDW BIT(6)
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#define MTL_DSP_REG_POLL_INTERVAL_US 10 /* 10 us */
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/* Memory windows */
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#define MTL_SRAM_WINDOW_OFFSET(x) (0x180000 + 0x8000 * (x))
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#define MTL_DSP_MBOX_UPLINK_OFFSET (MTL_SRAM_WINDOW_OFFSET(0) + 0x1000)
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#define MTL_DSP_MBOX_UPLINK_SIZE 0x1000
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#define MTL_DSP_MBOX_DOWNLINK_OFFSET MTL_SRAM_WINDOW_OFFSET(1)
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#define MTL_DSP_MBOX_DOWNLINK_SIZE 0x1000
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/* FW registers */
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#define MTL_DSP_ROM_STS MTL_SRAM_WINDOW_OFFSET(0) /* ROM status */
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#define MTL_DSP_ROM_ERROR (MTL_SRAM_WINDOW_OFFSET(0) + 0x4) /* ROM error code */
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#define MTL_DSP_REG_HFFLGPXQWY 0x163200 /* DSP core0 status */
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#define MTL_DSP_REG_HFFLGPXQWY_ERROR 0x163204 /* DSP core0 error */
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/* FSR status codes */
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#define FSR_STATE_ROM_RESET_VECTOR_DONE 0x8
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#define FSR_STATE_ROM_PURGE_BOOT 0x9
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#define FSR_STATE_ROM_RESTORE_BOOT 0xA
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#define FSR_STATE_ROM_FW_ENTRY_POINT 0xB
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#define FSR_STATE_ROM_VALIDATE_PUB_KEY 0xC
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#define FSR_STATE_ROM_POWER_DOWN_HPSRAM 0xD
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#define FSR_STATE_ROM_POWER_DOWN_ULPSRAM 0xE
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#define FSR_STATE_ROM_POWER_UP_ULPSRAM_STACK 0xF
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#define FSR_STATE_ROM_POWER_UP_HPSRAM_DMA 0x10
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#define FSR_STATE_ROM_BEFORE_EP_POINTER_READ 0x11
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#define FSR_STATE_ROM_VALIDATE_MANIFEST 0x12
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#define FSR_STATE_ROM_VALIDATE_FW_MODULE 0x13
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#define FSR_STATE_ROM_PROTECT_IMR_REGION 0x14
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#define FSR_STATE_ROM_PUSH_MODEL_ROUTINE 0x15
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#define FSR_STATE_ROM_PULL_MODEL_ROUTINE 0x16
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#define FSR_STATE_ROM_VALIDATE_PKG_DIR 0x17
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#define FSR_STATE_ROM_VALIDATE_CPD 0x18
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#define FSR_STATE_ROM_VALIDATE_CSS_MAN_HEADER 0x19
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#define FSR_STATE_ROM_VALIDATE_BLOB_SVN 0x1A
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#define FSR_STATE_ROM_VERIFY_IFWI_PARTITION 0x1B
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#define FSR_STATE_ROM_REMOVE_ACCESS_CONTROL 0x1C
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#define FSR_STATE_ROM_AUTH_BYPASS 0x1D
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#define FSR_STATE_ROM_AUTH_ENABLED 0x1E
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#define FSR_STATE_ROM_INIT_DMA 0x1F
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#define FSR_STATE_ROM_PURGE_FW_ENTRY 0x20
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#define FSR_STATE_ROM_PURGE_FW_END 0x21
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#define FSR_STATE_ROM_CLEAN_UP_BSS_DONE 0x22
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#define FSR_STATE_ROM_IMR_RESTORE_ENTRY 0x23
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#define FSR_STATE_ROM_IMR_RESTORE_END 0x24
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#define FSR_STATE_ROM_FW_MANIFEST_IN_DMA_BUFF 0x25
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#define FSR_STATE_ROM_LOAD_CSE_MAN_TO_IMR 0x26
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#define FSR_STATE_ROM_LOAD_FW_MAN_TO_IMR 0x27
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#define FSR_STATE_ROM_LOAD_FW_CODE_TO_IMR 0x28
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#define FSR_STATE_ROM_FW_LOADING_DONE 0x29
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#define FSR_STATE_ROM_FW_CODE_LOADED 0x2A
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#define FSR_STATE_ROM_VERIFY_IMAGE_TYPE 0x2B
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#define FSR_STATE_ROM_AUTH_API_INIT 0x2C
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#define FSR_STATE_ROM_AUTH_API_PROC 0x2D
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#define FSR_STATE_ROM_AUTH_API_FIRST_BUSY 0x2E
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#define FSR_STATE_ROM_AUTH_API_FIRST_RESULT 0x2F
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#define FSR_STATE_ROM_AUTH_API_CLEANUP 0x30
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#define MTL_DSP_REG_HfIMRIS1 0x162088
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#define MTL_DSP_REG_HfIMRIS1_IU_MASK BIT(0)
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bool mtl_dsp_check_ipc_irq(struct snd_sof_dev *sdev);
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int mtl_ipc_send_msg(struct snd_sof_dev *sdev, struct snd_sof_ipc_msg *msg);
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void mtl_enable_ipc_interrupts(struct snd_sof_dev *sdev);
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void mtl_disable_ipc_interrupts(struct snd_sof_dev *sdev);
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int mtl_enable_interrupts(struct snd_sof_dev *sdev, bool enable);
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int mtl_dsp_pre_fw_run(struct snd_sof_dev *sdev);
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int mtl_dsp_post_fw_run(struct snd_sof_dev *sdev);
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void mtl_dsp_dump(struct snd_sof_dev *sdev, u32 flags);
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int mtl_power_down_dsp(struct snd_sof_dev *sdev);
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int mtl_dsp_cl_init(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot);
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irqreturn_t mtl_ipc_irq_thread(int irq, void *context);
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int mtl_dsp_ipc_get_mailbox_offset(struct snd_sof_dev *sdev);
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int mtl_dsp_ipc_get_window_offset(struct snd_sof_dev *sdev, u32 id);
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void mtl_ipc_dump(struct snd_sof_dev *sdev);
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int mtl_dsp_core_get(struct snd_sof_dev *sdev, int core);
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int mtl_dsp_core_put(struct snd_sof_dev *sdev, int core);
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