125 lines
3.4 KiB
C
125 lines
3.4 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Device Tree binding constants for AST2700 reset controller.
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*
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* Copyright (c) 2024 Aspeed Technology Inc.
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*/
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#ifndef _MACH_ASPEED_AST2700_RESET_H_
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#define _MACH_ASPEED_AST2700_RESET_H_
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/* SOC0 */
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#define SCU0_RESET_SDRAM 0
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#define SCU0_RESET_DDRPHY 1
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#define SCU0_RESET_RSA 2
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#define SCU0_RESET_SHA3 3
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#define SCU0_RESET_HACE 4
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#define SCU0_RESET_SOC 5
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#define SCU0_RESET_VIDEO 6
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#define SCU0_RESET_2D 7
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#define SCU0_RESET_PCIS 8
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#define SCU0_RESET_RVAS0 9
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#define SCU0_RESET_RVAS1 10
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#define SCU0_RESET_SM3 11
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#define SCU0_RESET_SM4 12
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#define SCU0_RESET_CRT0 13
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#define SCU0_RESET_ECC 14
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#define SCU0_RESET_DP_PCI 15
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#define SCU0_RESET_UFS 16
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#define SCU0_RESET_EMMC 17
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#define SCU0_RESET_PCIE1RST 18
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#define SCU0_RESET_PCIE1RSTOE 19
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#define SCU0_RESET_PCIE0RST 20
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#define SCU0_RESET_PCIE0RSTOE 21
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#define SCU0_RESET_JTAG 22
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#define SCU0_RESET_MCTP0 23
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#define SCU0_RESET_MCTP1 24
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#define SCU0_RESET_XDMA0 25
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#define SCU0_RESET_XDMA1 26
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#define SCU0_RESET_H2X1 27
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#define SCU0_RESET_DP 28
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#define SCU0_RESET_DP_MCU 29
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#define SCU0_RESET_SSP 30
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#define SCU0_RESET_H2X0 31
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#define SCU0_RESET_PORTA_VHUB 32
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#define SCU0_RESET_PORTA_PHY3 33
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#define SCU0_RESET_PORTA_XHCI 34
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#define SCU0_RESET_PORTB_VHUB 35
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#define SCU0_RESET_PORTB_PHY3 36
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#define SCU0_RESET_PORTB_XHCI 37
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#define SCU0_RESET_PORTA_VHUB_EHCI 38
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#define SCU0_RESET_PORTB_VHUB_EHCI 39
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#define SCU0_RESET_UHCI 40
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#define SCU0_RESET_TSP 41
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#define SCU0_RESET_E2M0 42
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#define SCU0_RESET_E2M1 43
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#define SCU0_RESET_VLINK 44
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/* SOC1 */
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#define SCU1_RESET_LPC0 0
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#define SCU1_RESET_LPC1 1
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#define SCU1_RESET_MII 2
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#define SCU1_RESET_PECI 3
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#define SCU1_RESET_PWM 4
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#define SCU1_RESET_MAC0 5
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#define SCU1_RESET_MAC1 6
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#define SCU1_RESET_MAC2 7
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#define SCU1_RESET_ADC 8
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#define SCU1_RESET_SD 9
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#define SCU1_RESET_ESPI0 10
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#define SCU1_RESET_ESPI1 11
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#define SCU1_RESET_JTAG1 12
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#define SCU1_RESET_SPI0 13
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#define SCU1_RESET_SPI1 14
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#define SCU1_RESET_SPI2 15
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#define SCU1_RESET_I3C0 16
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#define SCU1_RESET_I3C1 17
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#define SCU1_RESET_I3C2 18
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#define SCU1_RESET_I3C3 19
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#define SCU1_RESET_I3C4 20
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#define SCU1_RESET_I3C5 21
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#define SCU1_RESET_I3C6 22
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#define SCU1_RESET_I3C7 23
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#define SCU1_RESET_I3C8 24
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#define SCU1_RESET_I3C9 25
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#define SCU1_RESET_I3C10 26
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#define SCU1_RESET_I3C11 27
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#define SCU1_RESET_I3C12 28
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#define SCU1_RESET_I3C13 29
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#define SCU1_RESET_I3C14 30
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#define SCU1_RESET_I3C15 31
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#define SCU1_RESET_MCU0 32
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#define SCU1_RESET_MCU1 33
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#define SCU1_RESET_H2A_SPI1 34
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#define SCU1_RESET_H2A_SPI2 35
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#define SCU1_RESET_UART0 36
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#define SCU1_RESET_UART1 37
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#define SCU1_RESET_UART2 38
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#define SCU1_RESET_UART3 39
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#define SCU1_RESET_I2C_FILTER 40
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#define SCU1_RESET_CALIPTRA 41
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#define SCU1_RESET_XDMA 42
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#define SCU1_RESET_FSI 43
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#define SCU1_RESET_CAN 44
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#define SCU1_RESET_MCTP 45
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#define SCU1_RESET_I2C 46
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#define SCU1_RESET_UART6 47
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#define SCU1_RESET_UART7 48
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#define SCU1_RESET_UART8 49
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#define SCU1_RESET_UART9 50
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#define SCU1_RESET_LTPI0 51
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#define SCU1_RESET_VGAL 52
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#define SCU1_RESET_LTPI1 53
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#define SCU1_RESET_ACE 54
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#define SCU1_RESET_E2M 55
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#define SCU1_RESET_UHCI 56
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#define SCU1_RESET_PORTC_USB2UART 57
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#define SCU1_RESET_PORTC_VHUB_EHCI 58
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#define SCU1_RESET_PORTD_USB2UART 59
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#define SCU1_RESET_PORTD_VHUB_EHCI 60
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#define SCU1_RESET_H2X 61
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#define SCU1_RESET_I3CDMA 62
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#define SCU1_RESET_PCIE2RST 63
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#endif /* _MACH_ASPEED_AST2700_RESET_H_ */
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