89 lines
2.5 KiB
C
89 lines
2.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
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#ifndef __DTS_MARVELL_PXA1908_CLOCK_H
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#define __DTS_MARVELL_PXA1908_CLOCK_H
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/* plls */
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#define PXA1908_CLK_CLK32 1
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#define PXA1908_CLK_VCTCXO 2
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#define PXA1908_CLK_PLL1_624 3
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#define PXA1908_CLK_PLL1_416 4
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#define PXA1908_CLK_PLL1_499 5
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#define PXA1908_CLK_PLL1_832 6
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#define PXA1908_CLK_PLL1_1248 7
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#define PXA1908_CLK_PLL1_D2 8
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#define PXA1908_CLK_PLL1_D4 9
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#define PXA1908_CLK_PLL1_D8 10
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#define PXA1908_CLK_PLL1_D16 11
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#define PXA1908_CLK_PLL1_D6 12
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#define PXA1908_CLK_PLL1_D12 13
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#define PXA1908_CLK_PLL1_D24 14
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#define PXA1908_CLK_PLL1_D48 15
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#define PXA1908_CLK_PLL1_D96 16
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#define PXA1908_CLK_PLL1_D13 17
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#define PXA1908_CLK_PLL1_32 18
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#define PXA1908_CLK_PLL1_208 19
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#define PXA1908_CLK_PLL1_117 20
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#define PXA1908_CLK_PLL1_416_GATE 21
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#define PXA1908_CLK_PLL1_624_GATE 22
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#define PXA1908_CLK_PLL1_832_GATE 23
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#define PXA1908_CLK_PLL1_1248_GATE 24
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#define PXA1908_CLK_PLL1_D2_GATE 25
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#define PXA1908_CLK_PLL1_499_EN 26
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#define PXA1908_CLK_PLL2VCO 27
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#define PXA1908_CLK_PLL2 28
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#define PXA1908_CLK_PLL2P 29
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#define PXA1908_CLK_PLL2VCODIV3 30
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#define PXA1908_CLK_PLL3VCO 31
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#define PXA1908_CLK_PLL3 32
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#define PXA1908_CLK_PLL3P 33
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#define PXA1908_CLK_PLL3VCODIV3 34
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#define PXA1908_CLK_PLL4VCO 35
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#define PXA1908_CLK_PLL4 36
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#define PXA1908_CLK_PLL4P 37
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#define PXA1908_CLK_PLL4VCODIV3 38
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/* apb (apbc) peripherals */
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#define PXA1908_CLK_UART0 1
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#define PXA1908_CLK_UART1 2
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#define PXA1908_CLK_GPIO 3
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#define PXA1908_CLK_PWM0 4
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#define PXA1908_CLK_PWM1 5
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#define PXA1908_CLK_PWM2 6
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#define PXA1908_CLK_PWM3 7
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#define PXA1908_CLK_SSP0 8
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#define PXA1908_CLK_SSP1 9
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#define PXA1908_CLK_IPC_RST 10
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#define PXA1908_CLK_RTC 11
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#define PXA1908_CLK_TWSI0 12
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#define PXA1908_CLK_KPC 13
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#define PXA1908_CLK_SWJTAG 14
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#define PXA1908_CLK_SSP2 15
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#define PXA1908_CLK_TWSI1 16
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#define PXA1908_CLK_THERMAL 17
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#define PXA1908_CLK_TWSI3 18
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/* apb (apbcp) peripherals */
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#define PXA1908_CLK_UART2 1
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#define PXA1908_CLK_TWSI2 2
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#define PXA1908_CLK_AICER 3
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/* axi (apmu) peripherals */
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#define PXA1908_CLK_CCIC1 1
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#define PXA1908_CLK_ISP 2
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#define PXA1908_CLK_DSI1 3
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#define PXA1908_CLK_DISP1 4
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#define PXA1908_CLK_CCIC0 5
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#define PXA1908_CLK_SDH0 6
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#define PXA1908_CLK_SDH1 7
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#define PXA1908_CLK_USB 8
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#define PXA1908_CLK_NF 9
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#define PXA1908_CLK_CORE_DEBUG 10
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#define PXA1908_CLK_VPU 11
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#define PXA1908_CLK_GC 12
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#define PXA1908_CLK_SDH2 13
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#define PXA1908_CLK_GC2D 14
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#define PXA1908_CLK_TRACE 15
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#define PXA1908_CLK_DVC_DFC_DEBUG 16
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#endif
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