176 lines
5.5 KiB
C
176 lines
5.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
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/* Copyright(c) 2024 Realtek Corporation
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*/
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#ifndef __RTW88XXA_H__
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#define __RTW88XXA_H__
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#include <asm/byteorder.h>
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#include "reg.h"
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struct rtw8821au_efuse {
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u8 res4[48]; /* 0xd0 */
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u8 vid[2]; /* 0x100 */
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u8 pid[2];
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u8 res8[3];
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u8 mac_addr[ETH_ALEN]; /* 0x107 */
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u8 res9[243];
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} __packed;
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struct rtw8812au_efuse {
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u8 vid[2]; /* 0xd0 */
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u8 pid[2]; /* 0xd2 */
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u8 res0[3];
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u8 mac_addr[ETH_ALEN]; /* 0xd7 */
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u8 res1[291];
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} __packed;
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struct rtw88xxa_efuse {
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__le16 rtl_id;
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u8 res0[6]; /* 0x02 */
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u8 usb_mode; /* 0x08 */
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u8 res1[7]; /* 0x09 */
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/* power index for four RF paths */
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struct rtw_txpwr_idx txpwr_idx_table[4];
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u8 channel_plan; /* 0xb8 */
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u8 xtal_k;
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u8 thermal_meter;
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u8 iqk_lck;
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u8 pa_type; /* 0xbc */
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u8 lna_type_2g; /* 0xbd */
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u8 res2;
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u8 lna_type_5g; /* 0xbf */
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u8 res3;
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u8 rf_board_option; /* 0xc1 */
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u8 rf_feature_option;
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u8 rf_bt_setting;
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u8 eeprom_version;
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u8 eeprom_customer_id; /* 0xc5 */
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u8 tx_bb_swing_setting_2g;
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u8 tx_bb_swing_setting_5g;
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u8 tx_pwr_calibrate_rate;
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u8 rf_antenna_option; /* 0xc9 */
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u8 rfe_option;
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u8 country_code[2];
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u8 res4[3];
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union {
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struct rtw8821au_efuse rtw8821au;
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struct rtw8812au_efuse rtw8812au;
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};
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} __packed;
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static_assert(sizeof(struct rtw88xxa_efuse) == 512);
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#define WLAN_BCN_DMA_TIME 0x02
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#define WLAN_TBTT_PROHIBIT 0x04
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#define WLAN_TBTT_HOLD_TIME 0x064
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#define WLAN_TBTT_TIME (WLAN_TBTT_PROHIBIT |\
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(WLAN_TBTT_HOLD_TIME << BIT_SHIFT_TBTT_HOLD_TIME_AP))
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struct rtw_jaguar_phy_status_rpt {
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__le32 w0;
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__le32 w1;
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__le32 w2;
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__le32 w3;
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__le32 w4;
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__le32 w5;
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__le32 w6;
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} __packed;
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#define RTW_JGRPHY_W0_GAIN_A GENMASK(6, 0)
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#define RTW_JGRPHY_W0_TRSW_A BIT(7)
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#define RTW_JGRPHY_W0_GAIN_B GENMASK(14, 8)
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#define RTW_JGRPHY_W0_TRSW_B BIT(15)
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#define RTW_JGRPHY_W0_CHL_NUM GENMASK(25, 16)
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#define RTW_JGRPHY_W0_SUB_CHNL GENMASK(29, 26)
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#define RTW_JGRPHY_W0_R_RFMOD GENMASK(31, 30)
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/* CCK: */
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#define RTW_JGRPHY_W1_SIG_QUAL GENMASK(7, 0)
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#define RTW_JGRPHY_W1_AGC_RPT_VGA_IDX GENMASK(12, 8)
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#define RTW_JGRPHY_W1_AGC_RPT_LNA_IDX GENMASK(15, 13)
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#define RTW_JGRPHY_W1_BB_POWER GENMASK(23, 16)
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/* OFDM: */
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#define RTW_JGRPHY_W1_PWDB_ALL GENMASK(7, 0)
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#define RTW_JGRPHY_W1_CFO_SHORT_A GENMASK(15, 8) /* s8 */
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#define RTW_JGRPHY_W1_CFO_SHORT_B GENMASK(23, 16) /* s8 */
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#define RTW_JGRPHY_W1_BT_RF_CH_MSB GENMASK(31, 30)
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#define RTW_JGRPHY_W2_ANT_DIV_SW_A BIT(0)
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#define RTW_JGRPHY_W2_ANT_DIV_SW_B BIT(1)
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#define RTW_JGRPHY_W2_BT_RF_CH_LSB GENMASK(7, 2)
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#define RTW_JGRPHY_W2_CFO_TAIL_A GENMASK(15, 8) /* s8 */
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#define RTW_JGRPHY_W2_CFO_TAIL_B GENMASK(23, 16) /* s8 */
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#define RTW_JGRPHY_W2_PCTS_MSK_RPT_0 GENMASK(31, 24)
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#define RTW_JGRPHY_W3_PCTS_MSK_RPT_1 GENMASK(7, 0)
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/* Stream 1 and 2 RX EVM: */
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#define RTW_JGRPHY_W3_RXEVM_1 GENMASK(15, 8) /* s8 */
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#define RTW_JGRPHY_W3_RXEVM_2 GENMASK(23, 16) /* s8 */
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#define RTW_JGRPHY_W3_RXSNR_A GENMASK(31, 24) /* s8 */
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#define RTW_JGRPHY_W4_RXSNR_B GENMASK(7, 0) /* s8 */
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#define RTW_JGRPHY_W4_PCTS_MSK_RPT_2 GENMASK(21, 8)
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#define RTW_JGRPHY_W4_PCTS_RPT_VALID BIT(22)
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#define RTW_JGRPHY_W4_RXEVM_3 GENMASK(31, 24) /* s8 */
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#define RTW_JGRPHY_W5_RXEVM_4 GENMASK(7, 0) /* s8 */
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/* 8812a, stream 1 and 2 CSI: */
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#define RTW_JGRPHY_W5_CSI_CURRENT_1 GENMASK(15, 8)
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#define RTW_JGRPHY_W5_CSI_CURRENT_2 GENMASK(23, 16)
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/* 8814a: */
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#define RTW_JGRPHY_W5_RXSNR_C GENMASK(15, 8) /* s8 */
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#define RTW_JGRPHY_W5_RXSNR_D GENMASK(23, 16) /* s8 */
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#define RTW_JGRPHY_W5_GAIN_C GENMASK(30, 24)
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#define RTW_JGRPHY_W5_TRSW_C BIT(31)
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#define RTW_JGRPHY_W6_GAIN_D GENMASK(6, 0)
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#define RTW_JGRPHY_W6_TRSW_D BIT(7)
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#define RTW_JGRPHY_W6_SIGEVM GENMASK(15, 8) /* s8 */
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#define RTW_JGRPHY_W6_ANTIDX_ANTC GENMASK(18, 16)
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#define RTW_JGRPHY_W6_ANTIDX_ANTD GENMASK(21, 19)
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#define RTW_JGRPHY_W6_DPDT_CTRL_KEEP BIT(22)
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#define RTW_JGRPHY_W6_GNT_BT_KEEP BIT(23)
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#define RTW_JGRPHY_W6_ANTIDX_ANTA GENMASK(26, 24)
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#define RTW_JGRPHY_W6_ANTIDX_ANTB GENMASK(29, 27)
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#define RTW_JGRPHY_W6_HW_ANTSW_OCCUR GENMASK(31, 30)
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#define RF18_BW_MASK (BIT(11) | BIT(10))
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void rtw88xxa_efuse_grant(struct rtw_dev *rtwdev, bool on);
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int rtw88xxa_read_efuse(struct rtw_dev *rtwdev, u8 *log_map);
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void rtw88xxa_power_off(struct rtw_dev *rtwdev,
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const struct rtw_pwr_seq_cmd *const *enter_lps_flow);
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int rtw88xxa_power_on(struct rtw_dev *rtwdev);
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u32 rtw88xxa_phy_read_rf(struct rtw_dev *rtwdev,
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enum rtw_rf_path rf_path, u32 addr, u32 mask);
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void rtw88xxa_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw,
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u8 primary_chan_idx);
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void rtw88xxa_query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status,
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struct rtw_rx_pkt_stat *pkt_stat,
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s8 (*cck_rx_pwr)(u8 lna_idx, u8 vga_idx));
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void rtw88xxa_set_tx_power_index(struct rtw_dev *rtwdev);
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void rtw88xxa_false_alarm_statistics(struct rtw_dev *rtwdev);
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void rtw88xxa_iqk_backup_mac_bb(struct rtw_dev *rtwdev,
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u32 *macbb_backup,
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const u32 *backup_macbb_reg,
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u32 macbb_num);
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void rtw88xxa_iqk_backup_afe(struct rtw_dev *rtwdev, u32 *afe_backup,
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const u32 *backup_afe_reg, u32 afe_num);
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void rtw88xxa_iqk_restore_mac_bb(struct rtw_dev *rtwdev,
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u32 *macbb_backup,
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const u32 *backup_macbb_reg,
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u32 macbb_num);
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void rtw88xxa_iqk_configure_mac(struct rtw_dev *rtwdev);
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bool rtw88xxa_iqk_finish(int average, int threshold,
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int *x_temp, int *y_temp, int *x, int *y,
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bool break_inner, bool break_outer);
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void rtw88xxa_phy_pwrtrack(struct rtw_dev *rtwdev,
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void (*do_lck)(struct rtw_dev *rtwdev),
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void (*do_iqk)(struct rtw_dev *rtwdev));
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void rtw88xxa_phy_cck_pd_set(struct rtw_dev *rtwdev, u8 new_lvl);
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#endif
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