154 lines
4.3 KiB
C
154 lines
4.3 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright 2023 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __AMDGPU_REG_STATE_H__
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#define __AMDGPU_REG_STATE_H__
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enum amdgpu_reg_state {
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AMDGPU_REG_STATE_TYPE_INVALID = 0,
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AMDGPU_REG_STATE_TYPE_XGMI = 1,
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AMDGPU_REG_STATE_TYPE_WAFL = 2,
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AMDGPU_REG_STATE_TYPE_PCIE = 3,
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AMDGPU_REG_STATE_TYPE_USR = 4,
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AMDGPU_REG_STATE_TYPE_USR_1 = 5
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};
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enum amdgpu_sysfs_reg_offset {
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AMDGPU_SYS_REG_STATE_XGMI = 0x0000,
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AMDGPU_SYS_REG_STATE_WAFL = 0x1000,
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AMDGPU_SYS_REG_STATE_PCIE = 0x2000,
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AMDGPU_SYS_REG_STATE_USR = 0x3000,
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AMDGPU_SYS_REG_STATE_USR_1 = 0x4000,
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AMDGPU_SYS_REG_STATE_END = 0x5000,
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};
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struct amdgpu_reg_state_header {
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uint16_t structure_size;
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uint8_t format_revision;
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uint8_t content_revision;
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uint8_t state_type;
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uint8_t num_instances;
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uint16_t pad;
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};
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enum amdgpu_reg_inst_state {
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AMDGPU_INST_S_OK,
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AMDGPU_INST_S_EDISABLED,
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AMDGPU_INST_S_EACCESS,
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};
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struct amdgpu_smn_reg_data {
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uint64_t addr;
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uint32_t value;
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uint32_t pad;
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};
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struct amdgpu_reg_inst_header {
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uint16_t instance;
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uint16_t state;
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uint16_t num_smn_regs;
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uint16_t pad;
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};
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struct amdgpu_regs_xgmi_v1_0 {
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struct amdgpu_reg_inst_header inst_header;
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struct amdgpu_smn_reg_data smn_reg_values[];
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};
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struct amdgpu_reg_state_xgmi_v1_0 {
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/* common_header.state_type must be AMDGPU_REG_STATE_TYPE_XGMI */
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struct amdgpu_reg_state_header common_header;
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struct amdgpu_regs_xgmi_v1_0 xgmi_state_regs[];
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};
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struct amdgpu_regs_wafl_v1_0 {
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struct amdgpu_reg_inst_header inst_header;
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struct amdgpu_smn_reg_data smn_reg_values[];
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};
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struct amdgpu_reg_state_wafl_v1_0 {
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/* common_header.state_type must be AMDGPU_REG_STATE_TYPE_WAFL */
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struct amdgpu_reg_state_header common_header;
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struct amdgpu_regs_wafl_v1_0 wafl_state_regs[];
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};
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struct amdgpu_regs_pcie_v1_0 {
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struct amdgpu_reg_inst_header inst_header;
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uint16_t device_status;
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uint16_t link_status;
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uint32_t sub_bus_number_latency;
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uint32_t pcie_corr_err_status;
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uint32_t pcie_uncorr_err_status;
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struct amdgpu_smn_reg_data smn_reg_values[];
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};
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struct amdgpu_reg_state_pcie_v1_0 {
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/* common_header.state_type must be AMDGPU_REG_STATE_TYPE_PCIE */
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struct amdgpu_reg_state_header common_header;
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struct amdgpu_regs_pcie_v1_0 pci_state_regs[];
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};
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struct amdgpu_regs_usr_v1_0 {
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struct amdgpu_reg_inst_header inst_header;
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struct amdgpu_smn_reg_data smn_reg_values[];
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};
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struct amdgpu_reg_state_usr_v1_0 {
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/* common_header.state_type must be AMDGPU_REG_STATE_TYPE_USR */
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struct amdgpu_reg_state_header common_header;
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struct amdgpu_regs_usr_v1_0 usr_state_regs[];
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};
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static inline size_t amdgpu_reginst_size(uint16_t num_inst, size_t inst_size,
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uint16_t num_regs)
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{
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return num_inst *
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(inst_size + num_regs * sizeof(struct amdgpu_smn_reg_data));
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}
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#define amdgpu_asic_get_reg_state_supported(adev) \
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(((adev)->asic_funcs && (adev)->asic_funcs->get_reg_state) ? 1 : 0)
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#define amdgpu_asic_get_reg_state(adev, state, buf, size) \
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((adev)->asic_funcs->get_reg_state ? \
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(adev)->asic_funcs->get_reg_state((adev), (state), (buf), \
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(size)) : \
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0)
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int amdgpu_reg_state_sysfs_init(struct amdgpu_device *adev);
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void amdgpu_reg_state_sysfs_fini(struct amdgpu_device *adev);
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#endif
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