58 lines
1.9 KiB
C
58 lines
1.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2022 Yassine Oudjana <y.oudjana@protonmail.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/platform_device.h>
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#include "clk-gate.h"
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#include "clk-mtk.h"
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#include <dt-bindings/clock/mediatek,mt6735-imgsys.h>
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#define IMG_CG_CON 0x00
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#define IMG_CG_SET 0x04
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#define IMG_CG_CLR 0x08
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static struct mtk_gate_regs imgsys_cg_regs = {
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.set_ofs = IMG_CG_SET,
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.clr_ofs = IMG_CG_CLR,
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.sta_ofs = IMG_CG_CON,
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};
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static const struct mtk_gate imgsys_gates[] = {
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GATE_MTK(CLK_IMG_SMI_LARB2, "smi_larb2", "mm_sel", &imgsys_cg_regs, 0, &mtk_clk_gate_ops_setclr),
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GATE_MTK(CLK_IMG_CAM_SMI, "cam_smi", "mm_sel", &imgsys_cg_regs, 5, &mtk_clk_gate_ops_setclr),
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GATE_MTK(CLK_IMG_CAM_CAM, "cam_cam", "mm_sel", &imgsys_cg_regs, 6, &mtk_clk_gate_ops_setclr),
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GATE_MTK(CLK_IMG_SEN_TG, "sen_tg", "mm_sel", &imgsys_cg_regs, 7, &mtk_clk_gate_ops_setclr),
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GATE_MTK(CLK_IMG_SEN_CAM, "sen_cam", "mm_sel", &imgsys_cg_regs, 8, &mtk_clk_gate_ops_setclr),
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GATE_MTK(CLK_IMG_CAM_SV, "cam_sv", "mm_sel", &imgsys_cg_regs, 9, &mtk_clk_gate_ops_setclr),
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GATE_MTK(CLK_IMG_SUFOD, "sufod", "mm_sel", &imgsys_cg_regs, 10, &mtk_clk_gate_ops_setclr),
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GATE_MTK(CLK_IMG_FD, "fd", "mm_sel", &imgsys_cg_regs, 11, &mtk_clk_gate_ops_setclr),
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};
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static const struct mtk_clk_desc imgsys_clks = {
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.clks = imgsys_gates,
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.num_clks = ARRAY_SIZE(imgsys_gates),
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};
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static const struct of_device_id of_match_mt6735_imgsys[] = {
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{ .compatible = "mediatek,mt6735-imgsys", .data = &imgsys_clks },
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{ /* sentinel */ }
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};
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static struct platform_driver clk_mt6735_imgsys = {
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.probe = mtk_clk_simple_probe,
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.remove = mtk_clk_simple_remove,
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.driver = {
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.name = "clk-mt6735-imgsys",
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.of_match_table = of_match_mt6735_imgsys,
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},
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};
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module_platform_driver(clk_mt6735_imgsys);
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MODULE_AUTHOR("Yassine Oudjana <y.oudjana@protonmail.com>");
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MODULE_DESCRIPTION("MediaTek MT6735 imgsys clock driver");
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MODULE_LICENSE("GPL");
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