87 lines
1.5 KiB
Plaintext
87 lines
1.5 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0 OR MIT
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/*
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* Copyright (C) 2024 Henry Bell <dmoo_dv@protonmail.com>
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*/
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/dts-v1/;
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#include "jh7110-common.dtsi"
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/ {
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model = "Pine64 Star64";
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compatible = "pine64,star64", "starfive,jh7110";
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aliases {
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ethernet1 = &gmac1;
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};
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};
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&gmac0 {
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starfive,tx-use-rgmii-clk;
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assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
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assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
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status = "okay";
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};
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&gmac1 {
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phy-handle = <&phy1>;
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phy-mode = "rgmii-id";
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starfive,tx-use-rgmii-clk;
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assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>;
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assigned-clock-parents = <&syscrg JH7110_SYSCLK_GMAC1_RMII_RTX>;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,dwmac-mdio";
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phy1: ethernet-phy@1 {
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reg = <1>;
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};
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};
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};
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&i2c0 {
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status = "okay";
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};
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&pcie1 {
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status = "okay";
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};
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&phy0 {
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rx-internal-delay-ps = <1500>;
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motorcomm,rx-clk-drv-microamp = <2910>;
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motorcomm,rx-data-drv-microamp = <2910>;
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motorcomm,tx-clk-adj-enabled;
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motorcomm,tx-clk-10-inverted;
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motorcomm,tx-clk-100-inverted;
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motorcomm,tx-clk-1000-inverted;
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};
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&phy1 {
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rx-internal-delay-ps = <0>;
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tx-internal-delay-ps = <300>;
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motorcomm,rx-clk-drv-microamp = <2910>;
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motorcomm,rx-data-drv-microamp = <2910>;
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motorcomm,tx-clk-adj-enabled;
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motorcomm,tx-clk-10-inverted;
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motorcomm,tx-clk-100-inverted;
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};
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&pwm {
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status = "okay";
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};
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&pwmdac {
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status = "okay";
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};
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&spi0 {
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status = "okay";
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};
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&usb0 {
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dr_mode = "peripheral";
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status = "okay";
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};
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