363 lines
8.6 KiB
Plaintext
363 lines
8.6 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
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* Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
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*/
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#include <dt-bindings/clock/sophgo,cv1800.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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cpus: cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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timebase-frequency = <25000000>;
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cpu0: cpu@0 {
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compatible = "thead,c906", "riscv";
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device_type = "cpu";
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reg = <0>;
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d-cache-block-size = <64>;
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d-cache-sets = <512>;
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d-cache-size = <65536>;
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i-cache-block-size = <64>;
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i-cache-sets = <128>;
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i-cache-size = <32768>;
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mmu-type = "riscv,sv39";
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riscv,isa = "rv64imafdc";
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
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"zifencei", "zihpm";
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cpu0_intc: interrupt-controller {
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compatible = "riscv,cpu-intc";
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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};
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osc: oscillator {
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compatible = "fixed-clock";
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clock-output-names = "osc_25m";
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#clock-cells = <0>;
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};
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soc {
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compatible = "simple-bus";
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interrupt-parent = <&plic>;
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#address-cells = <1>;
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#size-cells = <1>;
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dma-noncoherent;
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ranges;
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clk: clock-controller@3002000 {
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reg = <0x03002000 0x1000>;
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clocks = <&osc>;
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#clock-cells = <1>;
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};
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gpio0: gpio@3020000 {
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compatible = "snps,dw-apb-gpio";
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reg = <0x3020000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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porta: gpio-controller@0 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <32>;
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <60 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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gpio1: gpio@3021000 {
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compatible = "snps,dw-apb-gpio";
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reg = <0x3021000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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portb: gpio-controller@0 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <32>;
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <61 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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gpio2: gpio@3022000 {
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compatible = "snps,dw-apb-gpio";
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reg = <0x3022000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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portc: gpio-controller@0 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <32>;
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <62 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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gpio3: gpio@3023000 {
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compatible = "snps,dw-apb-gpio";
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reg = <0x3023000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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portd: gpio-controller@0 {
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compatible = "snps,dw-apb-gpio-port";
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gpio-controller;
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#gpio-cells = <2>;
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ngpios = <32>;
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <63 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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saradc: adc@30f0000 {
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compatible = "sophgo,cv1800b-saradc";
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reg = <0x030f0000 0x1000>;
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clocks = <&clk CLK_SARADC>;
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interrupts = <100 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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channel@0 {
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reg = <0>;
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};
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channel@1 {
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reg = <1>;
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};
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channel@2 {
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reg = <2>;
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};
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};
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i2c0: i2c@4000000 {
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compatible = "snps,designware-i2c";
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reg = <0x04000000 0x10000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C0>;
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clock-names = "ref", "pclk";
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interrupts = <49 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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i2c1: i2c@4010000 {
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compatible = "snps,designware-i2c";
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reg = <0x04010000 0x10000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C1>;
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clock-names = "ref", "pclk";
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interrupts = <50 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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i2c2: i2c@4020000 {
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compatible = "snps,designware-i2c";
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reg = <0x04020000 0x10000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C2>;
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clock-names = "ref", "pclk";
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interrupts = <51 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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i2c3: i2c@4030000 {
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compatible = "snps,designware-i2c";
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reg = <0x04030000 0x10000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C3>;
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clock-names = "ref", "pclk";
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interrupts = <52 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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i2c4: i2c@4040000 {
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compatible = "snps,designware-i2c";
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reg = <0x04040000 0x10000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clk CLK_I2C>, <&clk CLK_APB_I2C4>;
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clock-names = "ref", "pclk";
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interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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uart0: serial@4140000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x04140000 0x100>;
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interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk CLK_UART0>, <&clk CLK_APB_UART0>;
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clock-names = "baudclk", "apb_pclk";
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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uart1: serial@4150000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x04150000 0x100>;
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interrupts = <45 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk CLK_UART1>, <&clk CLK_APB_UART1>;
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clock-names = "baudclk", "apb_pclk";
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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uart2: serial@4160000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x04160000 0x100>;
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interrupts = <46 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk CLK_UART2>, <&clk CLK_APB_UART2>;
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clock-names = "baudclk", "apb_pclk";
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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uart3: serial@4170000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x04170000 0x100>;
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interrupts = <47 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk CLK_UART3>, <&clk CLK_APB_UART3>;
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clock-names = "baudclk", "apb_pclk";
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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spi0: spi@4180000 {
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compatible = "snps,dw-apb-ssi";
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reg = <0x04180000 0x10000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI0>;
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clock-names = "ssi_clk", "pclk";
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interrupts = <54 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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spi1: spi@4190000 {
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compatible = "snps,dw-apb-ssi";
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reg = <0x04190000 0x10000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI1>;
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clock-names = "ssi_clk", "pclk";
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interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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spi2: spi@41a0000 {
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compatible = "snps,dw-apb-ssi";
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reg = <0x041a0000 0x10000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI2>;
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clock-names = "ssi_clk", "pclk";
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interrupts = <56 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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spi3: spi@41b0000 {
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compatible = "snps,dw-apb-ssi";
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reg = <0x041b0000 0x10000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&clk CLK_SPI>, <&clk CLK_APB_SPI3>;
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clock-names = "ssi_clk", "pclk";
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interrupts = <57 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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uart4: serial@41c0000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x041c0000 0x100>;
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interrupts = <48 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk CLK_UART4>, <&clk CLK_APB_UART4>;
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clock-names = "baudclk", "apb_pclk";
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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sdhci0: mmc@4310000 {
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compatible = "sophgo,cv1800b-dwcmshc";
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reg = <0x4310000 0x1000>;
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interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk CLK_AXI4_SD0>,
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<&clk CLK_SD0>;
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clock-names = "core", "bus";
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status = "disabled";
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};
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sdhci1: mmc@4320000 {
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compatible = "sophgo,cv1800b-dwcmshc";
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reg = <0x4320000 0x1000>;
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interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk CLK_AXI4_SD1>,
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<&clk CLK_SD1>;
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clock-names = "core", "bus";
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status = "disabled";
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};
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dmac: dma-controller@4330000 {
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compatible = "snps,axi-dma-1.01a";
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reg = <0x04330000 0x1000>;
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interrupts = <29 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk CLK_SDMA_AXI>, <&clk CLK_SDMA_AXI>;
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clock-names = "core-clk", "cfgr-clk";
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#dma-cells = <1>;
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dma-channels = <8>;
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snps,block-size = <1024 1024 1024 1024
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1024 1024 1024 1024>;
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snps,priority = <0 1 2 3 4 5 6 7>;
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snps,dma-masters = <2>;
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snps,data-width = <4>;
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status = "disabled";
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};
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plic: interrupt-controller@70000000 {
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reg = <0x70000000 0x4000000>;
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interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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riscv,ndev = <101>;
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};
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clint: timer@74000000 {
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reg = <0x74000000 0x10000>;
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interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
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};
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};
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};
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