1028 lines
27 KiB
C
1028 lines
27 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2024 Loongson Technology Corporation Limited
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*/
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#include <asm/kvm_eiointc.h>
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#include <asm/kvm_vcpu.h>
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#include <linux/count_zeros.h>
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static void eiointc_set_sw_coreisr(struct loongarch_eiointc *s)
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{
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int ipnum, cpu, irq_index, irq_mask, irq;
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for (irq = 0; irq < EIOINTC_IRQS; irq++) {
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ipnum = s->ipmap.reg_u8[irq / 32];
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if (!(s->status & BIT(EIOINTC_ENABLE_INT_ENCODE))) {
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ipnum = count_trailing_zeros(ipnum);
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ipnum = (ipnum >= 0 && ipnum < 4) ? ipnum : 0;
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}
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irq_index = irq / 32;
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irq_mask = BIT(irq & 0x1f);
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cpu = s->coremap.reg_u8[irq];
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if (!!(s->coreisr.reg_u32[cpu][irq_index] & irq_mask))
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set_bit(irq, s->sw_coreisr[cpu][ipnum]);
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else
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clear_bit(irq, s->sw_coreisr[cpu][ipnum]);
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}
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}
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static void eiointc_update_irq(struct loongarch_eiointc *s, int irq, int level)
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{
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int ipnum, cpu, found, irq_index, irq_mask;
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struct kvm_vcpu *vcpu;
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struct kvm_interrupt vcpu_irq;
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ipnum = s->ipmap.reg_u8[irq / 32];
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if (!(s->status & BIT(EIOINTC_ENABLE_INT_ENCODE))) {
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ipnum = count_trailing_zeros(ipnum);
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ipnum = (ipnum >= 0 && ipnum < 4) ? ipnum : 0;
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}
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cpu = s->sw_coremap[irq];
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vcpu = kvm_get_vcpu(s->kvm, cpu);
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irq_index = irq / 32;
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irq_mask = BIT(irq & 0x1f);
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if (level) {
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/* if not enable return false */
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if (((s->enable.reg_u32[irq_index]) & irq_mask) == 0)
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return;
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s->coreisr.reg_u32[cpu][irq_index] |= irq_mask;
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found = find_first_bit(s->sw_coreisr[cpu][ipnum], EIOINTC_IRQS);
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set_bit(irq, s->sw_coreisr[cpu][ipnum]);
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} else {
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s->coreisr.reg_u32[cpu][irq_index] &= ~irq_mask;
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clear_bit(irq, s->sw_coreisr[cpu][ipnum]);
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found = find_first_bit(s->sw_coreisr[cpu][ipnum], EIOINTC_IRQS);
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}
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if (found < EIOINTC_IRQS)
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return; /* other irq is handling, needn't update parent irq */
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vcpu_irq.irq = level ? (INT_HWI0 + ipnum) : -(INT_HWI0 + ipnum);
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kvm_vcpu_ioctl_interrupt(vcpu, &vcpu_irq);
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}
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static inline void eiointc_update_sw_coremap(struct loongarch_eiointc *s,
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int irq, void *pvalue, u32 len, bool notify)
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{
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int i, cpu;
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u64 val = *(u64 *)pvalue;
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for (i = 0; i < len; i++) {
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cpu = val & 0xff;
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val = val >> 8;
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if (!(s->status & BIT(EIOINTC_ENABLE_CPU_ENCODE))) {
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cpu = ffs(cpu) - 1;
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cpu = (cpu >= 4) ? 0 : cpu;
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}
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if (s->sw_coremap[irq + i] == cpu)
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continue;
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if (notify && test_bit(irq + i, (unsigned long *)s->isr.reg_u8)) {
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/* lower irq at old cpu and raise irq at new cpu */
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eiointc_update_irq(s, irq + i, 0);
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s->sw_coremap[irq + i] = cpu;
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eiointc_update_irq(s, irq + i, 1);
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} else {
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s->sw_coremap[irq + i] = cpu;
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}
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}
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}
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void eiointc_set_irq(struct loongarch_eiointc *s, int irq, int level)
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{
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unsigned long flags;
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unsigned long *isr = (unsigned long *)s->isr.reg_u8;
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level ? set_bit(irq, isr) : clear_bit(irq, isr);
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spin_lock_irqsave(&s->lock, flags);
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eiointc_update_irq(s, irq, level);
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spin_unlock_irqrestore(&s->lock, flags);
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}
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static inline void eiointc_enable_irq(struct kvm_vcpu *vcpu,
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struct loongarch_eiointc *s, int index, u8 mask, int level)
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{
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u8 val;
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int irq;
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val = mask & s->isr.reg_u8[index];
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irq = ffs(val);
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while (irq != 0) {
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/*
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* enable bit change from 0 to 1,
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* need to update irq by pending bits
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*/
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eiointc_update_irq(s, irq - 1 + index * 8, level);
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val &= ~BIT(irq - 1);
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irq = ffs(val);
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}
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}
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static int loongarch_eiointc_readb(struct kvm_vcpu *vcpu, struct loongarch_eiointc *s,
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gpa_t addr, int len, void *val)
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{
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int index, ret = 0;
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u8 data = 0;
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gpa_t offset;
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offset = addr - EIOINTC_BASE;
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switch (offset) {
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case EIOINTC_NODETYPE_START ... EIOINTC_NODETYPE_END:
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index = offset - EIOINTC_NODETYPE_START;
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data = s->nodetype.reg_u8[index];
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break;
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case EIOINTC_IPMAP_START ... EIOINTC_IPMAP_END:
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index = offset - EIOINTC_IPMAP_START;
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data = s->ipmap.reg_u8[index];
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break;
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case EIOINTC_ENABLE_START ... EIOINTC_ENABLE_END:
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index = offset - EIOINTC_ENABLE_START;
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data = s->enable.reg_u8[index];
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break;
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case EIOINTC_BOUNCE_START ... EIOINTC_BOUNCE_END:
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index = offset - EIOINTC_BOUNCE_START;
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data = s->bounce.reg_u8[index];
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break;
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case EIOINTC_COREISR_START ... EIOINTC_COREISR_END:
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index = offset - EIOINTC_COREISR_START;
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data = s->coreisr.reg_u8[vcpu->vcpu_id][index];
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break;
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case EIOINTC_COREMAP_START ... EIOINTC_COREMAP_END:
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index = offset - EIOINTC_COREMAP_START;
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data = s->coremap.reg_u8[index];
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break;
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default:
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ret = -EINVAL;
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break;
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}
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*(u8 *)val = data;
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return ret;
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}
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static int loongarch_eiointc_readw(struct kvm_vcpu *vcpu, struct loongarch_eiointc *s,
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gpa_t addr, int len, void *val)
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{
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int index, ret = 0;
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u16 data = 0;
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gpa_t offset;
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offset = addr - EIOINTC_BASE;
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switch (offset) {
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case EIOINTC_NODETYPE_START ... EIOINTC_NODETYPE_END:
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index = (offset - EIOINTC_NODETYPE_START) >> 1;
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data = s->nodetype.reg_u16[index];
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break;
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case EIOINTC_IPMAP_START ... EIOINTC_IPMAP_END:
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index = (offset - EIOINTC_IPMAP_START) >> 1;
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data = s->ipmap.reg_u16[index];
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break;
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case EIOINTC_ENABLE_START ... EIOINTC_ENABLE_END:
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index = (offset - EIOINTC_ENABLE_START) >> 1;
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data = s->enable.reg_u16[index];
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break;
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case EIOINTC_BOUNCE_START ... EIOINTC_BOUNCE_END:
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index = (offset - EIOINTC_BOUNCE_START) >> 1;
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data = s->bounce.reg_u16[index];
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break;
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case EIOINTC_COREISR_START ... EIOINTC_COREISR_END:
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index = (offset - EIOINTC_COREISR_START) >> 1;
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data = s->coreisr.reg_u16[vcpu->vcpu_id][index];
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break;
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case EIOINTC_COREMAP_START ... EIOINTC_COREMAP_END:
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index = (offset - EIOINTC_COREMAP_START) >> 1;
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data = s->coremap.reg_u16[index];
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break;
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default:
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ret = -EINVAL;
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break;
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}
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*(u16 *)val = data;
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return ret;
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}
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static int loongarch_eiointc_readl(struct kvm_vcpu *vcpu, struct loongarch_eiointc *s,
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gpa_t addr, int len, void *val)
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{
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int index, ret = 0;
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u32 data = 0;
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gpa_t offset;
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offset = addr - EIOINTC_BASE;
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switch (offset) {
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case EIOINTC_NODETYPE_START ... EIOINTC_NODETYPE_END:
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index = (offset - EIOINTC_NODETYPE_START) >> 2;
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data = s->nodetype.reg_u32[index];
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break;
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case EIOINTC_IPMAP_START ... EIOINTC_IPMAP_END:
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index = (offset - EIOINTC_IPMAP_START) >> 2;
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data = s->ipmap.reg_u32[index];
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break;
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case EIOINTC_ENABLE_START ... EIOINTC_ENABLE_END:
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index = (offset - EIOINTC_ENABLE_START) >> 2;
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data = s->enable.reg_u32[index];
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break;
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case EIOINTC_BOUNCE_START ... EIOINTC_BOUNCE_END:
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index = (offset - EIOINTC_BOUNCE_START) >> 2;
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data = s->bounce.reg_u32[index];
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break;
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case EIOINTC_COREISR_START ... EIOINTC_COREISR_END:
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index = (offset - EIOINTC_COREISR_START) >> 2;
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data = s->coreisr.reg_u32[vcpu->vcpu_id][index];
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break;
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case EIOINTC_COREMAP_START ... EIOINTC_COREMAP_END:
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index = (offset - EIOINTC_COREMAP_START) >> 2;
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data = s->coremap.reg_u32[index];
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break;
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default:
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ret = -EINVAL;
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break;
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}
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*(u32 *)val = data;
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return ret;
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}
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static int loongarch_eiointc_readq(struct kvm_vcpu *vcpu, struct loongarch_eiointc *s,
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gpa_t addr, int len, void *val)
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{
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int index, ret = 0;
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u64 data = 0;
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gpa_t offset;
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offset = addr - EIOINTC_BASE;
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switch (offset) {
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case EIOINTC_NODETYPE_START ... EIOINTC_NODETYPE_END:
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index = (offset - EIOINTC_NODETYPE_START) >> 3;
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data = s->nodetype.reg_u64[index];
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break;
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case EIOINTC_IPMAP_START ... EIOINTC_IPMAP_END:
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index = (offset - EIOINTC_IPMAP_START) >> 3;
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data = s->ipmap.reg_u64;
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break;
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case EIOINTC_ENABLE_START ... EIOINTC_ENABLE_END:
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index = (offset - EIOINTC_ENABLE_START) >> 3;
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data = s->enable.reg_u64[index];
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break;
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case EIOINTC_BOUNCE_START ... EIOINTC_BOUNCE_END:
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index = (offset - EIOINTC_BOUNCE_START) >> 3;
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data = s->bounce.reg_u64[index];
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break;
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case EIOINTC_COREISR_START ... EIOINTC_COREISR_END:
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index = (offset - EIOINTC_COREISR_START) >> 3;
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data = s->coreisr.reg_u64[vcpu->vcpu_id][index];
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break;
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case EIOINTC_COREMAP_START ... EIOINTC_COREMAP_END:
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index = (offset - EIOINTC_COREMAP_START) >> 3;
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data = s->coremap.reg_u64[index];
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break;
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default:
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ret = -EINVAL;
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break;
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}
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*(u64 *)val = data;
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return ret;
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}
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static int kvm_eiointc_read(struct kvm_vcpu *vcpu,
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struct kvm_io_device *dev,
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gpa_t addr, int len, void *val)
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{
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int ret = -EINVAL;
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unsigned long flags;
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struct loongarch_eiointc *eiointc = vcpu->kvm->arch.eiointc;
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if (!eiointc) {
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kvm_err("%s: eiointc irqchip not valid!\n", __func__);
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return -EINVAL;
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}
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vcpu->kvm->stat.eiointc_read_exits++;
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spin_lock_irqsave(&eiointc->lock, flags);
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switch (len) {
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case 1:
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ret = loongarch_eiointc_readb(vcpu, eiointc, addr, len, val);
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break;
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case 2:
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ret = loongarch_eiointc_readw(vcpu, eiointc, addr, len, val);
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break;
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case 4:
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ret = loongarch_eiointc_readl(vcpu, eiointc, addr, len, val);
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break;
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case 8:
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ret = loongarch_eiointc_readq(vcpu, eiointc, addr, len, val);
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break;
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default:
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WARN_ONCE(1, "%s: Abnormal address access: addr 0x%llx, size %d\n",
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__func__, addr, len);
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}
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spin_unlock_irqrestore(&eiointc->lock, flags);
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return ret;
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}
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static int loongarch_eiointc_writeb(struct kvm_vcpu *vcpu,
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struct loongarch_eiointc *s,
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gpa_t addr, int len, const void *val)
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{
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int index, irq, bits, ret = 0;
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u8 cpu;
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u8 data, old_data;
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u8 coreisr, old_coreisr;
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gpa_t offset;
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data = *(u8 *)val;
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offset = addr - EIOINTC_BASE;
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switch (offset) {
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case EIOINTC_NODETYPE_START ... EIOINTC_NODETYPE_END:
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index = (offset - EIOINTC_NODETYPE_START);
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s->nodetype.reg_u8[index] = data;
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break;
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case EIOINTC_IPMAP_START ... EIOINTC_IPMAP_END:
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/*
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* ipmap cannot be set at runtime, can be set only at the beginning
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* of irqchip driver, need not update upper irq level
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*/
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index = (offset - EIOINTC_IPMAP_START);
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s->ipmap.reg_u8[index] = data;
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break;
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case EIOINTC_ENABLE_START ... EIOINTC_ENABLE_END:
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index = (offset - EIOINTC_ENABLE_START);
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old_data = s->enable.reg_u8[index];
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s->enable.reg_u8[index] = data;
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/*
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* 1: enable irq.
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* update irq when isr is set.
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*/
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data = s->enable.reg_u8[index] & ~old_data & s->isr.reg_u8[index];
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eiointc_enable_irq(vcpu, s, index, data, 1);
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/*
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* 0: disable irq.
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* update irq when isr is set.
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*/
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data = ~s->enable.reg_u8[index] & old_data & s->isr.reg_u8[index];
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eiointc_enable_irq(vcpu, s, index, data, 0);
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break;
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case EIOINTC_BOUNCE_START ... EIOINTC_BOUNCE_END:
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/* do not emulate hw bounced irq routing */
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index = offset - EIOINTC_BOUNCE_START;
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s->bounce.reg_u8[index] = data;
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break;
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case EIOINTC_COREISR_START ... EIOINTC_COREISR_END:
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index = (offset - EIOINTC_COREISR_START);
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/* use attrs to get current cpu index */
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cpu = vcpu->vcpu_id;
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coreisr = data;
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old_coreisr = s->coreisr.reg_u8[cpu][index];
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/* write 1 to clear interrupt */
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s->coreisr.reg_u8[cpu][index] = old_coreisr & ~coreisr;
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coreisr &= old_coreisr;
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bits = sizeof(data) * 8;
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irq = find_first_bit((void *)&coreisr, bits);
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while (irq < bits) {
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eiointc_update_irq(s, irq + index * bits, 0);
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bitmap_clear((void *)&coreisr, irq, 1);
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irq = find_first_bit((void *)&coreisr, bits);
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}
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break;
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case EIOINTC_COREMAP_START ... EIOINTC_COREMAP_END:
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irq = offset - EIOINTC_COREMAP_START;
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index = irq;
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s->coremap.reg_u8[index] = data;
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eiointc_update_sw_coremap(s, irq, (void *)&data, sizeof(data), true);
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break;
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default:
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ret = -EINVAL;
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break;
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}
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return ret;
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}
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static int loongarch_eiointc_writew(struct kvm_vcpu *vcpu,
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struct loongarch_eiointc *s,
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gpa_t addr, int len, const void *val)
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{
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int i, index, irq, bits, ret = 0;
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u8 cpu;
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u16 data, old_data;
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u16 coreisr, old_coreisr;
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gpa_t offset;
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data = *(u16 *)val;
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offset = addr - EIOINTC_BASE;
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switch (offset) {
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case EIOINTC_NODETYPE_START ... EIOINTC_NODETYPE_END:
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index = (offset - EIOINTC_NODETYPE_START) >> 1;
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s->nodetype.reg_u16[index] = data;
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break;
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case EIOINTC_IPMAP_START ... EIOINTC_IPMAP_END:
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/*
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* ipmap cannot be set at runtime, can be set only at the beginning
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* of irqchip driver, need not update upper irq level
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*/
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index = (offset - EIOINTC_IPMAP_START) >> 1;
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s->ipmap.reg_u16[index] = data;
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break;
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case EIOINTC_ENABLE_START ... EIOINTC_ENABLE_END:
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index = (offset - EIOINTC_ENABLE_START) >> 1;
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old_data = s->enable.reg_u32[index];
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s->enable.reg_u16[index] = data;
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/*
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* 1: enable irq.
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* update irq when isr is set.
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*/
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data = s->enable.reg_u16[index] & ~old_data & s->isr.reg_u16[index];
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index = index << 1;
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for (i = 0; i < sizeof(data); i++) {
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|
u8 mask = (data >> (i * 8)) & 0xff;
|
|
eiointc_enable_irq(vcpu, s, index + i, mask, 1);
|
|
}
|
|
/*
|
|
* 0: disable irq.
|
|
* update irq when isr is set.
|
|
*/
|
|
data = ~s->enable.reg_u16[index] & old_data & s->isr.reg_u16[index];
|
|
for (i = 0; i < sizeof(data); i++) {
|
|
u8 mask = (data >> (i * 8)) & 0xff;
|
|
eiointc_enable_irq(vcpu, s, index, mask, 0);
|
|
}
|
|
break;
|
|
case EIOINTC_BOUNCE_START ... EIOINTC_BOUNCE_END:
|
|
/* do not emulate hw bounced irq routing */
|
|
index = (offset - EIOINTC_BOUNCE_START) >> 1;
|
|
s->bounce.reg_u16[index] = data;
|
|
break;
|
|
case EIOINTC_COREISR_START ... EIOINTC_COREISR_END:
|
|
index = (offset - EIOINTC_COREISR_START) >> 1;
|
|
/* use attrs to get current cpu index */
|
|
cpu = vcpu->vcpu_id;
|
|
coreisr = data;
|
|
old_coreisr = s->coreisr.reg_u16[cpu][index];
|
|
/* write 1 to clear interrupt */
|
|
s->coreisr.reg_u16[cpu][index] = old_coreisr & ~coreisr;
|
|
coreisr &= old_coreisr;
|
|
bits = sizeof(data) * 8;
|
|
irq = find_first_bit((void *)&coreisr, bits);
|
|
while (irq < bits) {
|
|
eiointc_update_irq(s, irq + index * bits, 0);
|
|
bitmap_clear((void *)&coreisr, irq, 1);
|
|
irq = find_first_bit((void *)&coreisr, bits);
|
|
}
|
|
break;
|
|
case EIOINTC_COREMAP_START ... EIOINTC_COREMAP_END:
|
|
irq = offset - EIOINTC_COREMAP_START;
|
|
index = irq >> 1;
|
|
s->coremap.reg_u16[index] = data;
|
|
eiointc_update_sw_coremap(s, irq, (void *)&data, sizeof(data), true);
|
|
break;
|
|
default:
|
|
ret = -EINVAL;
|
|
break;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int loongarch_eiointc_writel(struct kvm_vcpu *vcpu,
|
|
struct loongarch_eiointc *s,
|
|
gpa_t addr, int len, const void *val)
|
|
{
|
|
int i, index, irq, bits, ret = 0;
|
|
u8 cpu;
|
|
u32 data, old_data;
|
|
u32 coreisr, old_coreisr;
|
|
gpa_t offset;
|
|
|
|
data = *(u32 *)val;
|
|
offset = addr - EIOINTC_BASE;
|
|
|
|
switch (offset) {
|
|
case EIOINTC_NODETYPE_START ... EIOINTC_NODETYPE_END:
|
|
index = (offset - EIOINTC_NODETYPE_START) >> 2;
|
|
s->nodetype.reg_u32[index] = data;
|
|
break;
|
|
case EIOINTC_IPMAP_START ... EIOINTC_IPMAP_END:
|
|
/*
|
|
* ipmap cannot be set at runtime, can be set only at the beginning
|
|
* of irqchip driver, need not update upper irq level
|
|
*/
|
|
index = (offset - EIOINTC_IPMAP_START) >> 2;
|
|
s->ipmap.reg_u32[index] = data;
|
|
break;
|
|
case EIOINTC_ENABLE_START ... EIOINTC_ENABLE_END:
|
|
index = (offset - EIOINTC_ENABLE_START) >> 2;
|
|
old_data = s->enable.reg_u32[index];
|
|
s->enable.reg_u32[index] = data;
|
|
/*
|
|
* 1: enable irq.
|
|
* update irq when isr is set.
|
|
*/
|
|
data = s->enable.reg_u32[index] & ~old_data & s->isr.reg_u32[index];
|
|
index = index << 2;
|
|
for (i = 0; i < sizeof(data); i++) {
|
|
u8 mask = (data >> (i * 8)) & 0xff;
|
|
eiointc_enable_irq(vcpu, s, index + i, mask, 1);
|
|
}
|
|
/*
|
|
* 0: disable irq.
|
|
* update irq when isr is set.
|
|
*/
|
|
data = ~s->enable.reg_u32[index] & old_data & s->isr.reg_u32[index];
|
|
for (i = 0; i < sizeof(data); i++) {
|
|
u8 mask = (data >> (i * 8)) & 0xff;
|
|
eiointc_enable_irq(vcpu, s, index, mask, 0);
|
|
}
|
|
break;
|
|
case EIOINTC_BOUNCE_START ... EIOINTC_BOUNCE_END:
|
|
/* do not emulate hw bounced irq routing */
|
|
index = (offset - EIOINTC_BOUNCE_START) >> 2;
|
|
s->bounce.reg_u32[index] = data;
|
|
break;
|
|
case EIOINTC_COREISR_START ... EIOINTC_COREISR_END:
|
|
index = (offset - EIOINTC_COREISR_START) >> 2;
|
|
/* use attrs to get current cpu index */
|
|
cpu = vcpu->vcpu_id;
|
|
coreisr = data;
|
|
old_coreisr = s->coreisr.reg_u32[cpu][index];
|
|
/* write 1 to clear interrupt */
|
|
s->coreisr.reg_u32[cpu][index] = old_coreisr & ~coreisr;
|
|
coreisr &= old_coreisr;
|
|
bits = sizeof(data) * 8;
|
|
irq = find_first_bit((void *)&coreisr, bits);
|
|
while (irq < bits) {
|
|
eiointc_update_irq(s, irq + index * bits, 0);
|
|
bitmap_clear((void *)&coreisr, irq, 1);
|
|
irq = find_first_bit((void *)&coreisr, bits);
|
|
}
|
|
break;
|
|
case EIOINTC_COREMAP_START ... EIOINTC_COREMAP_END:
|
|
irq = offset - EIOINTC_COREMAP_START;
|
|
index = irq >> 2;
|
|
s->coremap.reg_u32[index] = data;
|
|
eiointc_update_sw_coremap(s, irq, (void *)&data, sizeof(data), true);
|
|
break;
|
|
default:
|
|
ret = -EINVAL;
|
|
break;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int loongarch_eiointc_writeq(struct kvm_vcpu *vcpu,
|
|
struct loongarch_eiointc *s,
|
|
gpa_t addr, int len, const void *val)
|
|
{
|
|
int i, index, irq, bits, ret = 0;
|
|
u8 cpu;
|
|
u64 data, old_data;
|
|
u64 coreisr, old_coreisr;
|
|
gpa_t offset;
|
|
|
|
data = *(u64 *)val;
|
|
offset = addr - EIOINTC_BASE;
|
|
|
|
switch (offset) {
|
|
case EIOINTC_NODETYPE_START ... EIOINTC_NODETYPE_END:
|
|
index = (offset - EIOINTC_NODETYPE_START) >> 3;
|
|
s->nodetype.reg_u64[index] = data;
|
|
break;
|
|
case EIOINTC_IPMAP_START ... EIOINTC_IPMAP_END:
|
|
/*
|
|
* ipmap cannot be set at runtime, can be set only at the beginning
|
|
* of irqchip driver, need not update upper irq level
|
|
*/
|
|
index = (offset - EIOINTC_IPMAP_START) >> 3;
|
|
s->ipmap.reg_u64 = data;
|
|
break;
|
|
case EIOINTC_ENABLE_START ... EIOINTC_ENABLE_END:
|
|
index = (offset - EIOINTC_ENABLE_START) >> 3;
|
|
old_data = s->enable.reg_u64[index];
|
|
s->enable.reg_u64[index] = data;
|
|
/*
|
|
* 1: enable irq.
|
|
* update irq when isr is set.
|
|
*/
|
|
data = s->enable.reg_u64[index] & ~old_data & s->isr.reg_u64[index];
|
|
index = index << 3;
|
|
for (i = 0; i < sizeof(data); i++) {
|
|
u8 mask = (data >> (i * 8)) & 0xff;
|
|
eiointc_enable_irq(vcpu, s, index + i, mask, 1);
|
|
}
|
|
/*
|
|
* 0: disable irq.
|
|
* update irq when isr is set.
|
|
*/
|
|
data = ~s->enable.reg_u64[index] & old_data & s->isr.reg_u64[index];
|
|
for (i = 0; i < sizeof(data); i++) {
|
|
u8 mask = (data >> (i * 8)) & 0xff;
|
|
eiointc_enable_irq(vcpu, s, index, mask, 0);
|
|
}
|
|
break;
|
|
case EIOINTC_BOUNCE_START ... EIOINTC_BOUNCE_END:
|
|
/* do not emulate hw bounced irq routing */
|
|
index = (offset - EIOINTC_BOUNCE_START) >> 3;
|
|
s->bounce.reg_u64[index] = data;
|
|
break;
|
|
case EIOINTC_COREISR_START ... EIOINTC_COREISR_END:
|
|
index = (offset - EIOINTC_COREISR_START) >> 3;
|
|
/* use attrs to get current cpu index */
|
|
cpu = vcpu->vcpu_id;
|
|
coreisr = data;
|
|
old_coreisr = s->coreisr.reg_u64[cpu][index];
|
|
/* write 1 to clear interrupt */
|
|
s->coreisr.reg_u64[cpu][index] = old_coreisr & ~coreisr;
|
|
coreisr &= old_coreisr;
|
|
bits = sizeof(data) * 8;
|
|
irq = find_first_bit((void *)&coreisr, bits);
|
|
while (irq < bits) {
|
|
eiointc_update_irq(s, irq + index * bits, 0);
|
|
bitmap_clear((void *)&coreisr, irq, 1);
|
|
irq = find_first_bit((void *)&coreisr, bits);
|
|
}
|
|
break;
|
|
case EIOINTC_COREMAP_START ... EIOINTC_COREMAP_END:
|
|
irq = offset - EIOINTC_COREMAP_START;
|
|
index = irq >> 3;
|
|
s->coremap.reg_u64[index] = data;
|
|
eiointc_update_sw_coremap(s, irq, (void *)&data, sizeof(data), true);
|
|
break;
|
|
default:
|
|
ret = -EINVAL;
|
|
break;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int kvm_eiointc_write(struct kvm_vcpu *vcpu,
|
|
struct kvm_io_device *dev,
|
|
gpa_t addr, int len, const void *val)
|
|
{
|
|
int ret = -EINVAL;
|
|
unsigned long flags;
|
|
struct loongarch_eiointc *eiointc = vcpu->kvm->arch.eiointc;
|
|
|
|
if (!eiointc) {
|
|
kvm_err("%s: eiointc irqchip not valid!\n", __func__);
|
|
return -EINVAL;
|
|
}
|
|
|
|
vcpu->kvm->stat.eiointc_write_exits++;
|
|
spin_lock_irqsave(&eiointc->lock, flags);
|
|
switch (len) {
|
|
case 1:
|
|
ret = loongarch_eiointc_writeb(vcpu, eiointc, addr, len, val);
|
|
break;
|
|
case 2:
|
|
ret = loongarch_eiointc_writew(vcpu, eiointc, addr, len, val);
|
|
break;
|
|
case 4:
|
|
ret = loongarch_eiointc_writel(vcpu, eiointc, addr, len, val);
|
|
break;
|
|
case 8:
|
|
ret = loongarch_eiointc_writeq(vcpu, eiointc, addr, len, val);
|
|
break;
|
|
default:
|
|
WARN_ONCE(1, "%s: Abnormal address access: addr 0x%llx, size %d\n",
|
|
__func__, addr, len);
|
|
}
|
|
spin_unlock_irqrestore(&eiointc->lock, flags);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static const struct kvm_io_device_ops kvm_eiointc_ops = {
|
|
.read = kvm_eiointc_read,
|
|
.write = kvm_eiointc_write,
|
|
};
|
|
|
|
static int kvm_eiointc_virt_read(struct kvm_vcpu *vcpu,
|
|
struct kvm_io_device *dev,
|
|
gpa_t addr, int len, void *val)
|
|
{
|
|
unsigned long flags;
|
|
u32 *data = val;
|
|
struct loongarch_eiointc *eiointc = vcpu->kvm->arch.eiointc;
|
|
|
|
if (!eiointc) {
|
|
kvm_err("%s: eiointc irqchip not valid!\n", __func__);
|
|
return -EINVAL;
|
|
}
|
|
|
|
addr -= EIOINTC_VIRT_BASE;
|
|
spin_lock_irqsave(&eiointc->lock, flags);
|
|
switch (addr) {
|
|
case EIOINTC_VIRT_FEATURES:
|
|
*data = eiointc->features;
|
|
break;
|
|
case EIOINTC_VIRT_CONFIG:
|
|
*data = eiointc->status;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
spin_unlock_irqrestore(&eiointc->lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int kvm_eiointc_virt_write(struct kvm_vcpu *vcpu,
|
|
struct kvm_io_device *dev,
|
|
gpa_t addr, int len, const void *val)
|
|
{
|
|
int ret = 0;
|
|
unsigned long flags;
|
|
u32 value = *(u32 *)val;
|
|
struct loongarch_eiointc *eiointc = vcpu->kvm->arch.eiointc;
|
|
|
|
if (!eiointc) {
|
|
kvm_err("%s: eiointc irqchip not valid!\n", __func__);
|
|
return -EINVAL;
|
|
}
|
|
|
|
addr -= EIOINTC_VIRT_BASE;
|
|
spin_lock_irqsave(&eiointc->lock, flags);
|
|
switch (addr) {
|
|
case EIOINTC_VIRT_FEATURES:
|
|
ret = -EPERM;
|
|
break;
|
|
case EIOINTC_VIRT_CONFIG:
|
|
/*
|
|
* eiointc features can only be set at disabled status
|
|
*/
|
|
if ((eiointc->status & BIT(EIOINTC_ENABLE)) && value) {
|
|
ret = -EPERM;
|
|
break;
|
|
}
|
|
eiointc->status = value & eiointc->features;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
spin_unlock_irqrestore(&eiointc->lock, flags);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static const struct kvm_io_device_ops kvm_eiointc_virt_ops = {
|
|
.read = kvm_eiointc_virt_read,
|
|
.write = kvm_eiointc_virt_write,
|
|
};
|
|
|
|
static int kvm_eiointc_ctrl_access(struct kvm_device *dev,
|
|
struct kvm_device_attr *attr)
|
|
{
|
|
int ret = 0;
|
|
unsigned long flags;
|
|
unsigned long type = (unsigned long)attr->attr;
|
|
u32 i, start_irq;
|
|
void __user *data;
|
|
struct loongarch_eiointc *s = dev->kvm->arch.eiointc;
|
|
|
|
data = (void __user *)attr->addr;
|
|
spin_lock_irqsave(&s->lock, flags);
|
|
switch (type) {
|
|
case KVM_DEV_LOONGARCH_EXTIOI_CTRL_INIT_NUM_CPU:
|
|
if (copy_from_user(&s->num_cpu, data, 4))
|
|
ret = -EFAULT;
|
|
break;
|
|
case KVM_DEV_LOONGARCH_EXTIOI_CTRL_INIT_FEATURE:
|
|
if (copy_from_user(&s->features, data, 4))
|
|
ret = -EFAULT;
|
|
if (!(s->features & BIT(EIOINTC_HAS_VIRT_EXTENSION)))
|
|
s->status |= BIT(EIOINTC_ENABLE);
|
|
break;
|
|
case KVM_DEV_LOONGARCH_EXTIOI_CTRL_LOAD_FINISHED:
|
|
eiointc_set_sw_coreisr(s);
|
|
for (i = 0; i < (EIOINTC_IRQS / 4); i++) {
|
|
start_irq = i * 4;
|
|
eiointc_update_sw_coremap(s, start_irq,
|
|
(void *)&s->coremap.reg_u32[i], sizeof(u32), false);
|
|
}
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
spin_unlock_irqrestore(&s->lock, flags);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int kvm_eiointc_regs_access(struct kvm_device *dev,
|
|
struct kvm_device_attr *attr,
|
|
bool is_write)
|
|
{
|
|
int addr, cpuid, offset, ret = 0;
|
|
unsigned long flags;
|
|
void *p = NULL;
|
|
void __user *data;
|
|
struct loongarch_eiointc *s;
|
|
|
|
s = dev->kvm->arch.eiointc;
|
|
addr = attr->attr;
|
|
cpuid = addr >> 16;
|
|
addr &= 0xffff;
|
|
data = (void __user *)attr->addr;
|
|
switch (addr) {
|
|
case EIOINTC_NODETYPE_START ... EIOINTC_NODETYPE_END:
|
|
offset = (addr - EIOINTC_NODETYPE_START) / 4;
|
|
p = &s->nodetype.reg_u32[offset];
|
|
break;
|
|
case EIOINTC_IPMAP_START ... EIOINTC_IPMAP_END:
|
|
offset = (addr - EIOINTC_IPMAP_START) / 4;
|
|
p = &s->ipmap.reg_u32[offset];
|
|
break;
|
|
case EIOINTC_ENABLE_START ... EIOINTC_ENABLE_END:
|
|
offset = (addr - EIOINTC_ENABLE_START) / 4;
|
|
p = &s->enable.reg_u32[offset];
|
|
break;
|
|
case EIOINTC_BOUNCE_START ... EIOINTC_BOUNCE_END:
|
|
offset = (addr - EIOINTC_BOUNCE_START) / 4;
|
|
p = &s->bounce.reg_u32[offset];
|
|
break;
|
|
case EIOINTC_ISR_START ... EIOINTC_ISR_END:
|
|
offset = (addr - EIOINTC_ISR_START) / 4;
|
|
p = &s->isr.reg_u32[offset];
|
|
break;
|
|
case EIOINTC_COREISR_START ... EIOINTC_COREISR_END:
|
|
offset = (addr - EIOINTC_COREISR_START) / 4;
|
|
p = &s->coreisr.reg_u32[cpuid][offset];
|
|
break;
|
|
case EIOINTC_COREMAP_START ... EIOINTC_COREMAP_END:
|
|
offset = (addr - EIOINTC_COREMAP_START) / 4;
|
|
p = &s->coremap.reg_u32[offset];
|
|
break;
|
|
default:
|
|
kvm_err("%s: unknown eiointc register, addr = %d\n", __func__, addr);
|
|
return -EINVAL;
|
|
}
|
|
|
|
spin_lock_irqsave(&s->lock, flags);
|
|
if (is_write) {
|
|
if (copy_from_user(p, data, 4))
|
|
ret = -EFAULT;
|
|
} else {
|
|
if (copy_to_user(data, p, 4))
|
|
ret = -EFAULT;
|
|
}
|
|
spin_unlock_irqrestore(&s->lock, flags);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int kvm_eiointc_sw_status_access(struct kvm_device *dev,
|
|
struct kvm_device_attr *attr,
|
|
bool is_write)
|
|
{
|
|
int addr, ret = 0;
|
|
unsigned long flags;
|
|
void *p = NULL;
|
|
void __user *data;
|
|
struct loongarch_eiointc *s;
|
|
|
|
s = dev->kvm->arch.eiointc;
|
|
addr = attr->attr;
|
|
addr &= 0xffff;
|
|
|
|
data = (void __user *)attr->addr;
|
|
switch (addr) {
|
|
case KVM_DEV_LOONGARCH_EXTIOI_SW_STATUS_NUM_CPU:
|
|
p = &s->num_cpu;
|
|
break;
|
|
case KVM_DEV_LOONGARCH_EXTIOI_SW_STATUS_FEATURE:
|
|
p = &s->features;
|
|
break;
|
|
case KVM_DEV_LOONGARCH_EXTIOI_SW_STATUS_STATE:
|
|
p = &s->status;
|
|
break;
|
|
default:
|
|
kvm_err("%s: unknown eiointc register, addr = %d\n", __func__, addr);
|
|
return -EINVAL;
|
|
}
|
|
spin_lock_irqsave(&s->lock, flags);
|
|
if (is_write) {
|
|
if (copy_from_user(p, data, 4))
|
|
ret = -EFAULT;
|
|
} else {
|
|
if (copy_to_user(data, p, 4))
|
|
ret = -EFAULT;
|
|
}
|
|
spin_unlock_irqrestore(&s->lock, flags);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int kvm_eiointc_get_attr(struct kvm_device *dev,
|
|
struct kvm_device_attr *attr)
|
|
{
|
|
switch (attr->group) {
|
|
case KVM_DEV_LOONGARCH_EXTIOI_GRP_REGS:
|
|
return kvm_eiointc_regs_access(dev, attr, false);
|
|
case KVM_DEV_LOONGARCH_EXTIOI_GRP_SW_STATUS:
|
|
return kvm_eiointc_sw_status_access(dev, attr, false);
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
|
|
static int kvm_eiointc_set_attr(struct kvm_device *dev,
|
|
struct kvm_device_attr *attr)
|
|
{
|
|
switch (attr->group) {
|
|
case KVM_DEV_LOONGARCH_EXTIOI_GRP_CTRL:
|
|
return kvm_eiointc_ctrl_access(dev, attr);
|
|
case KVM_DEV_LOONGARCH_EXTIOI_GRP_REGS:
|
|
return kvm_eiointc_regs_access(dev, attr, true);
|
|
case KVM_DEV_LOONGARCH_EXTIOI_GRP_SW_STATUS:
|
|
return kvm_eiointc_sw_status_access(dev, attr, true);
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
|
|
static int kvm_eiointc_create(struct kvm_device *dev, u32 type)
|
|
{
|
|
int ret;
|
|
struct loongarch_eiointc *s;
|
|
struct kvm_io_device *device, *device1;
|
|
struct kvm *kvm = dev->kvm;
|
|
|
|
/* eiointc has been created */
|
|
if (kvm->arch.eiointc)
|
|
return -EINVAL;
|
|
|
|
s = kzalloc(sizeof(struct loongarch_eiointc), GFP_KERNEL);
|
|
if (!s)
|
|
return -ENOMEM;
|
|
|
|
spin_lock_init(&s->lock);
|
|
s->kvm = kvm;
|
|
|
|
/*
|
|
* Initialize IOCSR device
|
|
*/
|
|
device = &s->device;
|
|
kvm_iodevice_init(device, &kvm_eiointc_ops);
|
|
mutex_lock(&kvm->slots_lock);
|
|
ret = kvm_io_bus_register_dev(kvm, KVM_IOCSR_BUS,
|
|
EIOINTC_BASE, EIOINTC_SIZE, device);
|
|
mutex_unlock(&kvm->slots_lock);
|
|
if (ret < 0) {
|
|
kfree(s);
|
|
return ret;
|
|
}
|
|
|
|
device1 = &s->device_vext;
|
|
kvm_iodevice_init(device1, &kvm_eiointc_virt_ops);
|
|
ret = kvm_io_bus_register_dev(kvm, KVM_IOCSR_BUS,
|
|
EIOINTC_VIRT_BASE, EIOINTC_VIRT_SIZE, device1);
|
|
if (ret < 0) {
|
|
kvm_io_bus_unregister_dev(kvm, KVM_IOCSR_BUS, &s->device);
|
|
kfree(s);
|
|
return ret;
|
|
}
|
|
kvm->arch.eiointc = s;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void kvm_eiointc_destroy(struct kvm_device *dev)
|
|
{
|
|
struct kvm *kvm;
|
|
struct loongarch_eiointc *eiointc;
|
|
|
|
if (!dev || !dev->kvm || !dev->kvm->arch.eiointc)
|
|
return;
|
|
|
|
kvm = dev->kvm;
|
|
eiointc = kvm->arch.eiointc;
|
|
kvm_io_bus_unregister_dev(kvm, KVM_IOCSR_BUS, &eiointc->device);
|
|
kvm_io_bus_unregister_dev(kvm, KVM_IOCSR_BUS, &eiointc->device_vext);
|
|
kfree(eiointc);
|
|
}
|
|
|
|
static struct kvm_device_ops kvm_eiointc_dev_ops = {
|
|
.name = "kvm-loongarch-eiointc",
|
|
.create = kvm_eiointc_create,
|
|
.destroy = kvm_eiointc_destroy,
|
|
.set_attr = kvm_eiointc_set_attr,
|
|
.get_attr = kvm_eiointc_get_attr,
|
|
};
|
|
|
|
int kvm_loongarch_register_eiointc_device(void)
|
|
{
|
|
return kvm_register_device_ops(&kvm_eiointc_dev_ops, KVM_DEV_TYPE_LOONGARCH_EIOINTC);
|
|
}
|